Eeschema: Add gEDA/Lepton EDA importer

Add a schematic importer for gEDA and Lepton EDA .sch files.
The importer parses the full gEDA file format including
components, nets, buses, attributes, text, graphical
primitives, and paths with bezier curves.

A builtin symbol library ships 39 standard gEDA symbols so
import works without a gEDA installation. Symbol resolution
follows an 11-step search chain matching native gEDA/Lepton
conventions across environment variables, system paths, XDG
directories, RC files, config files, and project directories.
Last-found-wins priority matches native gEDA behavior.

RC file parsing handles gafrc and gschemrc component-library
directives. Lepton-EDA INI configs (lepton.conf, geda.conf)
are also parsed.

Project import reads gEDA .prj files and discovers schematics
and PCBs automatically.

File format knowledge and embedded symbol definitions derived
from gEDA/gaf (C) 1998-2010 Ales Hvezda, 1998-2016 gEDA
Contributors, and Lepton EDA (C) 2017-2024 Lepton EDA
Contributors. Both licensed under GNU GPL v2 or later.

common/wildcards_and_files_ext.cpp

@@ -309,6 +309,12 @@ wxString FILEEXT::PADSProjectFilesWildcard()
 }
 
 
+wxString FILEEXT::GedaProjectFilesWildcard()
+{
+    return _( "gEDA / Lepton EDA project files" ) + AddFileExtListToFilter( { "prj", "sch", "pcb" } );
+}
+
+
 wxString FILEEXT::OrCadPcb2NetlistFileWildcard()
 {
     return _( "OrcadPCB2 netlist files" )

eeschema/CMakeLists.txt

@@ -64,6 +64,9 @@ set( EESCHEMA_SCH_IO
     # Database IO plugin
     sch_io/database/sch_io_database.cpp
 
+    # gEDA IO plugin
+    sch_io/geda/sch_io_geda.cpp
+
     # Eagle IO plugin
     sch_io/eagle/sch_io_eagle.cpp
 

eeschema/files-io.cpp

@@ -1470,6 +1470,7 @@ bool SCH_EDIT_FRAME::importFile( const wxString& aFileName, int aFileType,
     case SCH_IO_MGR::SCH_EASYEDA:
     case SCH_IO_MGR::SCH_EASYEDAPRO:
     case SCH_IO_MGR::SCH_PADS:
+    case SCH_IO_MGR::SCH_GEDA:
     {
         // We insist on caller sending us an absolute path, if it does not, we say it's a bug.
         // Unless we are passing the files in aproperties, in which case aFileName can be empty.

eeschema/sch_io/geda/sch_io_geda.h

@@ -0,0 +1,365 @@
+/*
+ * This program source code file is part of KiCad, a free EDA CAD application.
+ *
+ * Copyright The KiCad Developers, see AUTHORS.txt for contributors.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version 3
+ * of the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program.  If not, see <http://www.gnu.org/licenses/>.
+ *
+ * This file contains file format knowledge derived from the gEDA and
+ * Lepton EDA projects:
+ *
+ *   gEDA/gaf  - Copyright (C) 1998-2010 Ales Hvezda
+ *               Copyright (C) 1998-2016 gEDA Contributors
+ *   Lepton EDA - Copyright (C) 2017-2024 Lepton EDA Contributors
+ *
+ * Both projects are licensed under the GNU General Public License v2 or later.
+ * See https://github.com/lepton-eda/lepton-eda and
+ *     https://github.com/rlutz/geda-gaf
+ */
+
+#ifndef SCH_IO_GEDA_H_
+#define SCH_IO_GEDA_H_
+
+#include <sch_io/sch_io.h>
+#include <sch_io/sch_io_mgr.h>
+
+#include <eda_shape.h>
+#include <stroke_params.h>
+
+#include <wx/filename.h>
+#include <wx/textfile.h>
+
+#include <map>
+#include <set>
+#include <vector>
+#include <memory>
+
+class LIB_SYMBOL;
+class SCH_SHEET;
+class SCH_SCREEN;
+class SCH_SYMBOL;
+class SCH_LINE;
+class SCH_TEXT;
+class SCH_SHAPE;
+class SCH_JUNCTION;
+class SCH_NO_CONNECT;
+class SCH_PIN;
+class SCHEMATIC;
+
+
+/**
+ * A #SCH_IO derivation for loading gEDA/gschem schematic files (.sch).
+ *
+ * gEDA schematics are ASCII text files with a simple line-oriented format.
+ * Each object type is identified by the first character of its definition line:
+ *   C=component, N=net, U=bus, P=pin, T=text, L=line, B=box, V=circle,
+ *   A=arc, H=path, G=picture, {=attributes, [=embedded component.
+ *
+ * Symbol loading follows the sch-rnd model: .sym files are discovered by
+ * scanning standard gEDA library directories and loaded on first reference.
+ * Embedded symbols (defined inline via [] blocks) are also supported.
+ */
+class SCH_IO_GEDA : public SCH_IO
+{
+public:
+    SCH_IO_GEDA();
+    ~SCH_IO_GEDA() override;
+
+    const IO_BASE::IO_FILE_DESC GetSchematicFileDesc() const override
+    {
+        return IO_BASE::IO_FILE_DESC( _HKI( "gEDA / Lepton EDA schematic files" ), { "sch" } );
+    }
+
+    const IO_BASE::IO_FILE_DESC GetLibraryDesc() const override
+    {
+        return IO_BASE::IO_FILE_DESC( wxEmptyString, {} );
+    }
+
+    bool CanReadSchematicFile( const wxString& aFileName ) const override;
+
+    int GetModifyHash() const override { return 0; }
+
+    SCH_SHEET* LoadSchematicFile( const wxString& aFileName, SCHEMATIC* aSchematic,
+                                  SCH_SHEET*                            aAppendToMe = nullptr,
+                                  const std::map<std::string, UTF8>*    aProperties = nullptr ) override;
+
+    bool IsLibraryWritable( const wxString& aLibraryPath ) override { return false; }
+
+    /// Return the map of built-in gEDA symbol definitions (symbol name -> .sym content).
+    static const std::map<wxString, wxString>& getBuiltinSymbols();
+
+private:
+    // -----------------------------------------------------------------------
+    // Data types
+    // -----------------------------------------------------------------------
+
+    /// Parsed attribute from a gEDA T line inside a { } block.
+    struct GEDA_ATTR
+    {
+        wxString name;
+        wxString value;
+        int      x        = 0;
+        int      y        = 0;
+        int      size     = 10;
+        int      angle    = 0;
+        int      align    = 0;
+        bool     visible  = false;
+        int      showNV   = 0;   ///< 0=name+value, 1=value, 2=name
+    };
+
+    /// Pending component waiting for symbol resolution.
+    /// A gEDA C line defers actual symbol loading until we know whether
+    /// the definition is embedded ([] block) or from the library.
+    struct PENDING_COMPONENT
+    {
+        wxString                basename;
+        int                     x           = 0;
+        int                     y           = 0;
+        int                     angle       = 0;
+        int                     mirror      = 0;
+        int                     selectable  = 1;
+        std::vector<GEDA_ATTR>  attrs;
+        bool                    embedded    = false;
+        std::unique_ptr<LIB_SYMBOL> embeddedSym;
+    };
+
+    /// Entry in the symbol library search cache.
+    struct SYM_CACHE_ENTRY
+    {
+        wxString                    path;       ///< Full path to .sym file
+        std::unique_ptr<LIB_SYMBOL> symbol;     ///< Loaded symbol (null if not yet loaded)
+        wxString                    symversion;  ///< symversion from the .sym file (if any)
+        wxString                    netAttr;    ///< net= attribute (e.g. "GND:1") identifying power symbols
+    };
+
+    // -----------------------------------------------------------------------
+    // Coordinate transformation
+    // -----------------------------------------------------------------------
+
+    /// gEDA coordinates are mils with Y-up. KiCad uses 100nm IU with Y-down.
+    /// During parsing we store raw gEDA coordinates, then post-process to flip Y.
+    static constexpr int MILS_TO_IU = 254;
+
+    /// Convert a gEDA distance in mils to KiCad IU.
+    int toKiCadDist( int aMils ) const;
+
+    /// Apply the Y-flip and scale to transform gEDA coords to KiCad.
+    /// Call only after m_maxY has been computed in the post-processing pass.
+    VECTOR2I toKiCad( int aGedaX, int aGedaY ) const;
+
+    // -----------------------------------------------------------------------
+    // File parsing
+    // -----------------------------------------------------------------------
+
+    /// Parse the "v YYYYMMDD N" version line and validate.
+    bool parseVersionLine( const wxString& aLine );
+
+    /// Read a { } attribute block starting after the '{' line.
+    std::vector<GEDA_ATTR> parseAttributes( wxTextFile& aFile, size_t& aLineIdx );
+
+    /// Find an attribute by name, returns empty string if not found.
+    wxString findAttr( const std::vector<GEDA_ATTR>& aAttrs, const wxString& aName ) const;
+
+    /// Find a GEDA_ATTR struct by name, returns nullptr if not found.
+    const GEDA_ATTR* findAttrStruct( const std::vector<GEDA_ATTR>& aAttrs,
+                                      const wxString& aName ) const;
+
+    /// Check for and consume a { } attribute block at the current line position.
+    std::vector<GEDA_ATTR> maybeParseAttributes( wxTextFile& aFile, size_t& aLineIdx );
+
+    // -----------------------------------------------------------------------
+    // Object parsers - schematics
+    // -----------------------------------------------------------------------
+
+    void parseComponent( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseNet( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseBus( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseText( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseLine( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseBox( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseCircle( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseArc( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parsePath( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parsePicture( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parsePin( const wxString& aLine, wxTextFile& aFile, size_t& aLineIdx );
+    void parseEmbeddedComponent( wxTextFile& aFile, size_t& aLineIdx );
+
+    // -----------------------------------------------------------------------
+    // Symbol loading
+    // -----------------------------------------------------------------------
+
+    /// Ensure the symbol library hash is built by scanning gEDA library dirs.
+    void initSymbolLibrary();
+
+    /// Recursively scan a directory for .sym files and populate m_symLibrary.
+    void scanSymbolDir( const wxString& aDir );
+
+    /// Parse an RC file (gafrc or gschemrc) for component-library directives.
+    void parseRcFileForLibraries( const wxString& aPath, const wxString& aBaseDir );
+
+    /// Load a .sym file and return a LIB_SYMBOL. Parses the symbol format
+    /// which is the same as schematic format but contains P/L/A/V/B/T/H
+    /// objects within a symbol context.
+    /// If aSymversion is non-null, the symbol's symversion attribute (if present) is written to it.
+    /// If aNetAttr is non-null, the symbol's net= attribute (if present) is written to it.
+    std::unique_ptr<LIB_SYMBOL> loadSymbolFile( const wxString& aPath,
+                                                 wxString* aSymversion = nullptr,
+                                                 wxString* aNetAttr = nullptr );
+
+    /// Parse objects from a .sym file or [] block into a LIB_SYMBOL.
+    void parseSymbolObjects( wxTextFile& aFile, size_t& aLineIdx, LIB_SYMBOL& aSymbol,
+                             size_t aEndLine );
+
+    /// Create a pin on a LIB_SYMBOL from gEDA P line data and its attributes.
+    void addSymbolPin( LIB_SYMBOL& aSymbol, int aX1, int aY1, int aX2, int aY2,
+                       int aWhichEnd, const std::vector<GEDA_ATTR>& aAttrs );
+
+    /// Add a graphical item (line/box/circle/arc/path) to a LIB_SYMBOL.
+    void addSymbolGraphic( LIB_SYMBOL& aSymbol, const wxString& aLine, wxTextFile& aFile,
+                           size_t& aLineIdx, wxChar aType );
+
+    /// Instantiate the pending component: look up or load the symbol,
+    /// create SCH_SYMBOL, apply transforms and attributes, and emit to screen.
+    void flushPendingComponent();
+
+    /// Import a gEDA hierarchical sub-schematic as a KiCad SCH_SHEET.
+    /// Called when a component has a source= attribute.
+    void importHierarchicalSheet( const wxString& aSourceFile );
+
+    /// Get or load a cached symbol by gEDA basename.
+    LIB_SYMBOL* getOrLoadSymbol( const wxString& aBasename );
+
+    /// Try loading a symbol from the built-in standard library embedded in the importer.
+    std::unique_ptr<LIB_SYMBOL> loadBuiltinSymbol( const wxString& aBasename );
+
+    /// Create a fallback rectangular symbol when the .sym file is not found.
+    std::unique_ptr<LIB_SYMBOL> createFallbackSymbol( const wxString& aBasename );
+
+    /// Map gEDA angle (0/90/180/270) + mirror to KiCad symbol orientation.
+    int toKiCadOrientation( int aAngle, int aMirror ) const;
+
+    /// Derive the KiCad import library name from the schematic file.
+    wxString getLibName() const;
+
+    // -----------------------------------------------------------------------
+    // Style mapping
+    // -----------------------------------------------------------------------
+
+    /// Map gEDA dashstyle (0-4) to KiCad LINE_STYLE.
+    static LINE_STYLE toLineStyle( int aDashStyle );
+
+    /// Map gEDA filltype (0-4) to KiCad FILL_T.
+    static FILL_T toFillType( int aFillType );
+
+    // -----------------------------------------------------------------------
+    // Post-processing
+    // -----------------------------------------------------------------------
+
+    /// Track a point as a net or pin endpoint for junction detection.
+    void trackEndpoint( int aGedaX, int aGedaY );
+
+    /// Run the full post-processing pipeline after parsing is complete:
+    /// 1. Flush any pending component
+    /// 2. Compute bounding box and Y-flip all coordinates
+    /// 3. Process net= attributes for implicit connections
+    /// 4. Place junctions where 3+ endpoints meet
+    void postProcess();
+
+    /// For each component with net= attributes, create global labels at pin positions.
+    void processNetAttributes();
+
+    /// Place junctions where 3+ net/pin endpoints coincide.
+    void addJunctions();
+
+    /// Create SCH_BUS_WIRE_ENTRY objects where net endpoints touch bus segments.
+    void addBusEntries();
+
+    /// Load sub-schematics for any SCH_SHEET objects created during parsing.
+    void loadDeferredSheets();
+
+    /// Enlarge the page if needed and center all content on the sheet.
+    void fitPageToContent();
+
+    // -----------------------------------------------------------------------
+    // State
+    // -----------------------------------------------------------------------
+
+    SCH_SCREEN*  m_screen;
+    SCH_SHEET*   m_rootSheet;
+    SCHEMATIC*   m_schematic;
+    wxFileName   m_filename;
+
+    /// The maximum Y coordinate seen during parsing (gEDA coords, before flip).
+    int m_maxY;
+
+    /// gEDA file version fields from the "v YYYYMMDD N" header line.
+    /// Used for version-aware parsing of old format files.
+    long m_releaseVersion;
+    long m_fileFormatVersion;
+
+    /// Pending component awaiting symbol resolution.
+    std::unique_ptr<PENDING_COMPONENT> m_pendingComp;
+
+    /// Symbol library cache: gEDA basename -> cache entry.
+    std::map<wxString, SYM_CACHE_ENTRY> m_symLibrary;
+    bool m_symLibraryInitialized;
+
+    /// Loaded symbols for this import session, keyed by basename.
+    std::map<wxString, std::unique_ptr<LIB_SYMBOL>> m_libSymbols;
+
+    /// Sequential counter for auto-generated #PWR references.
+    int m_powerCounter;
+
+    /// Net endpoint positions in raw gEDA coordinates for junction detection.
+    std::map<std::pair<int,int>, int> m_netEndpoints;
+
+    /// Components with net= attributes that need post-processing.
+    struct NET_ATTR_RECORD
+    {
+        wxString netname;
+        wxString pinnumber;
+        SCH_SYMBOL* symbol;
+    };
+
+    std::vector<NET_ATTR_RECORD> m_netAttrRecords;
+
+    /// Parsed bus segment in KiCad coordinates with gEDA ripper direction.
+    struct BUS_SEGMENT
+    {
+        VECTOR2I start;
+        VECTOR2I end;
+        int      ripperDir;  ///< -1, 0, or 1 from gEDA U line
+    };
+
+    std::vector<BUS_SEGMENT> m_busSegments;
+
+    /// Deferred hierarchical sheet loads. Populated during parsing when components
+    /// with source= attributes are found, processed after the main parse completes.
+    struct DEFERRED_SHEET
+    {
+        SCH_SHEET* sheet;
+        wxString   sourceFile;  ///< Resolved full path to the sub-schematic
+    };
+
+    std::vector<DEFERRED_SHEET> m_deferredSheets;
+
+    /// Set of fully-resolved file paths currently in the import call stack,
+    /// used to detect and prevent circular hierarchy references.
+    std::set<wxString> m_importStack;
+
+    /// Properties passed from the import framework (search paths, etc.)
+    const std::map<std::string, UTF8>* m_properties;
+};
+
+#endif // SCH_IO_GEDA_H_

eeschema/sch_io/sch_io_mgr.cpp

@@ -32,6 +32,7 @@
 #include <sch_io/cadstar/sch_io_cadstar_archive.h>
 #include <sch_io/easyeda/sch_io_easyeda.h>
 #include <sch_io/easyedapro/sch_io_easyedapro.h>
+#include <sch_io/geda/sch_io_geda.h>
 #include <sch_io/database/sch_io_database.h>
 #include <sch_io/ltspice/sch_io_ltspice.h>
 #include <sch_io/http_lib/sch_io_http_lib.h>
@@ -75,6 +76,7 @@ SCH_IO* SCH_IO_MGR::FindPlugin( SCH_FILE_T aFileType )
     case SCH_EAGLE:           return new SCH_IO_EAGLE();
     case SCH_EASYEDA:         return new SCH_IO_EASYEDA();
     case SCH_EASYEDAPRO:      return new SCH_IO_EASYEDAPRO();
+    case SCH_GEDA:            return new SCH_IO_GEDA();
     case SCH_LTSPICE:         return new SCH_IO_LTSPICE();
     case SCH_HTTP:            return new SCH_IO_HTTP_LIB();
     case SCH_PADS:            return new SCH_IO_PADS();
@@ -99,6 +101,7 @@ const wxString SCH_IO_MGR::ShowType( SCH_FILE_T aType )
     case SCH_EAGLE:           return wxString( wxT( "EAGLE" ) );
     case SCH_EASYEDA:         return wxString( wxT( "EasyEDA (JLCEDA) Std" ) );
     case SCH_EASYEDAPRO:      return wxString( wxT( "EasyEDA (JLCEDA) Pro" ) );
+    case SCH_GEDA:            return wxString( wxT( "gEDA / Lepton EDA" ) );
     case SCH_LTSPICE:         return wxString( wxT( "LTspice" ) );
     case SCH_HTTP:            return wxString( wxT( "HTTP" ) );
     case SCH_PADS:            return wxString( wxT( "PADS Logic" ) );
@@ -130,6 +133,8 @@ SCH_IO_MGR::SCH_FILE_T SCH_IO_MGR::EnumFromStr( const wxString& aType )
         return SCH_EASYEDA;
     else if( aType == wxT( "EasyEDA (JLCEDA) Pro" ) )
         return SCH_EASYEDAPRO;
+    else if( aType == wxT( "gEDA / Lepton EDA" ) )
+        return SCH_GEDA;
     else if( aType == wxT( "LTspice" ) )
         return SCH_LTSPICE;
     else if( aType == wxT( "HTTP" ) )

eeschema/sch_io/sch_io_mgr.h

@@ -65,6 +65,7 @@ public:
         SCH_EAGLE,            ///< Autodesk Eagle file format
         SCH_EASYEDA,          ///< EasyEDA Std schematic file
         SCH_EASYEDAPRO,       ///< EasyEDA Pro archive
+        SCH_GEDA,             ///< gEDA/gschem schematic format
         SCH_LTSPICE,          ///< LtSpice Schematic format
         SCH_HTTP,             ///< KiCad HTTP library
         SCH_PADS,             ///< PADS Logic schematic format

include/wildcards_and_files_ext.h

@@ -253,6 +253,7 @@ public:
     static wxString AltiumProjectFilesWildcard();
     static wxString EagleFilesWildcard();
     static wxString PADSProjectFilesWildcard();
+    static wxString GedaProjectFilesWildcard();
     static wxString EasyEdaArchiveWildcard();
     static wxString EasyEdaProFileWildcard();
     static wxString PdfFileWildcard();

kicad/import_proj.cpp

@@ -25,7 +25,11 @@
 #include <richio.h>
 
 #include <wx/fileconf.h>
+#include <wx/filedlg.h>
 #include <wx/msgdlg.h>
+#include <wx/tokenzr.h>
+#include <wx/dir.h>
+#include <wx/textfile.h>
 #include <wx/wfstream.h>
 
 #include <kiway.h>
@@ -330,6 +334,252 @@ void IMPORT_PROJ_HELPER::ImportPadsFiles()
 }
 
 
+void IMPORT_PROJ_HELPER::GedaProjectHandler()
+{
+    wxFileName prjFile = m_InputFile;
+
+    if( prjFile.GetExt().CmpNoCase( "prj" ) != 0 )
+        return;
+
+    wxTextFile file;
+
+    if( !file.Open( prjFile.GetFullPath() ) )
+    {
+        wxLogWarning( _( "Could not open gEDA / Lepton EDA project file '%s'." ), prjFile.GetFullPath() );
+        return;
+    }
+
+    std::vector<wxFileName> schFiles;
+    wxString                outputName;
+    wxString                elementsDir;
+
+    for( size_t i = 0; i < file.GetLineCount(); ++i )
+    {
+        wxString line = file.GetLine( i );
+
+        line.Trim( true );
+        line.Trim( false );
+
+        if( line.IsEmpty() )
+            continue;
+
+        if( line.StartsWith( wxT( "#" ) ) || line.StartsWith( wxT( ";" ) ) )
+            continue;
+
+        int commentPos = line.Find( wxT( "#" ) );
+
+        if( commentPos != wxNOT_FOUND )
+        {
+            line = line.Left( commentPos );
+            line.Trim( true );
+            line.Trim( false );
+        }
+
+        if( line.IsEmpty() )
+            continue;
+
+        wxStringTokenizer tok( line );
+
+        if( !tok.HasMoreTokens() )
+            continue;
+
+        wxString keyword = tok.GetNextToken();
+
+        if( keyword.CmpNoCase( "schematics" ) == 0 )
+        {
+            while( tok.HasMoreTokens() )
+            {
+                wxString  schToken = tok.GetNextToken();
+                wxFileName schFile( schToken );
+
+                if( !schFile.IsAbsolute() )
+                    schFile.MakeAbsolute( prjFile.GetPath() );
+
+                schFiles.push_back( schFile );
+            }
+        }
+        else if( keyword.CmpNoCase( "output-name" ) == 0 )
+        {
+            wxString rest = line.Mid( keyword.length() );
+            rest.Trim( true );
+            rest.Trim( false );
+            outputName = rest;
+        }
+        else if( keyword.CmpNoCase( "elements-dir" ) == 0 )
+        {
+            wxString rest = line.Mid( keyword.length() );
+            rest.Trim( true );
+            rest.Trim( false );
+            elementsDir = rest;
+        }
+    }
+
+    if( !elementsDir.IsEmpty() )
+    {
+        wxFileName elementsPath( elementsDir );
+
+        if( !elementsPath.IsAbsolute() )
+            elementsPath.MakeAbsolute( prjFile.GetPath() );
+
+        m_properties["elements_dir"] = elementsPath.GetFullPath().ToStdString();
+    }
+
+    if( schFiles.empty() )
+    {
+        wxFileName candidate = prjFile;
+        candidate.SetExt( wxS( "sch" ) );
+
+        if( candidate.FileExists() )
+            schFiles.push_back( candidate );
+    }
+
+    auto promptForMissingFile =
+            [&]( const wxString& aTitle, const wxString& aWildcard, wxFileName& aFile ) -> bool
+            {
+                wxString defaultDir = aFile.GetPath();
+
+                if( defaultDir.IsEmpty() )
+                    defaultDir = prjFile.GetPath();
+
+                wxFileDialog dlg( m_frame, aTitle, defaultDir, wxEmptyString, aWildcard,
+                                  wxFD_OPEN | wxFD_FILE_MUST_EXIST );
+
+                if( dlg.ShowModal() == wxID_OK )
+                {
+                    aFile.Assign( dlg.GetPath() );
+                    return true;
+                }
+
+                aFile.Clear();
+                return false;
+            };
+
+    std::vector<wxFileName> resolvedSchFiles;
+    const wxString          schWildcard = _( "gEDA / Lepton EDA schematic files" ) + wxS( " (*.sch)|*.sch" );
+
+    for( wxFileName schFile : schFiles )
+    {
+        if( !schFile.FileExists() )
+        {
+            if( !promptForMissingFile( _( "Locate gEDA / Lepton EDA Schematic" ), schWildcard, schFile ) )
+                continue;
+        }
+
+        resolvedSchFiles.push_back( schFile );
+    }
+
+    if( schFiles.empty() && resolvedSchFiles.empty() )
+    {
+        wxFileName schFile;
+
+        if( promptForMissingFile( _( "Locate gEDA / Lepton EDA Schematic" ), schWildcard, schFile ) )
+            resolvedSchFiles.push_back( schFile );
+    }
+
+    if( resolvedSchFiles.size() > 1 )
+    {
+        // Pass additional schematic files as a semicolon-delimited property so the
+        // importer can create sub-sheets for each additional page within a single
+        // KiCad project hierarchy.
+        wxString additionalFiles;
+
+        for( size_t i = 1; i < resolvedSchFiles.size(); i++ )
+        {
+            if( !additionalFiles.IsEmpty() )
+                additionalFiles += wxT( ";" );
+
+            additionalFiles += resolvedSchFiles[i].GetFullPath();
+        }
+
+        m_properties["additional_schematics"] = additionalFiles.ToStdString();
+    }
+
+    // Auto-discover subdirectories containing .sym files and pass them as
+    // additional search paths for the importer's symbol resolution.
+    auto discoverSymDirs = [&]( const wxString& aBaseDir, wxString& aSymPaths )
+    {
+        wxDir dir( aBaseDir );
+
+        if( !dir.IsOpened() )
+            return;
+
+        wxString subdir;
+        bool     cont = dir.GetFirst( &subdir, wxEmptyString, wxDIR_DIRS );
+
+        while( cont )
+        {
+            wxString subdirPath = aBaseDir + wxFileName::GetPathSeparator() + subdir;
+            wxDir    childDir( subdirPath );
+
+            if( childDir.IsOpened() && childDir.HasFiles( wxT( "*.sym" ) ) )
+            {
+                if( !aSymPaths.IsEmpty() )
+                    aSymPaths += wxT( "\n" );
+
+                aSymPaths += subdirPath;
+            }
+
+            cont = dir.GetNext( &subdir );
+        }
+    };
+
+    wxString symPaths;
+    discoverSymDirs( prjFile.GetPath(), symPaths );
+
+    if( !resolvedSchFiles.empty() )
+    {
+        wxString schDir = resolvedSchFiles[0].GetPath();
+
+        if( schDir != prjFile.GetPath() )
+            discoverSymDirs( schDir, symPaths );
+    }
+
+    if( !symPaths.IsEmpty() )
+        m_properties["sym_search_paths"] = symPaths.ToStdString();
+
+    if( !resolvedSchFiles.empty() )
+        doImport( resolvedSchFiles[0].GetFullPath(), FRAME_SCH, SCH_IO_MGR::SCH_GEDA );
+
+    wxFileName layoutDir( prjFile.GetPath(), wxEmptyString );
+    layoutDir.RemoveLastDir();
+    layoutDir.AppendDir( wxS( "layout" ) );
+
+    wxFileName pcbFile;
+
+    if( !outputName.IsEmpty() )
+    {
+        wxFileName candidate( layoutDir.GetPath(), outputName, wxS( "pcb" ) );
+
+        if( candidate.FileExists() )
+            pcbFile = candidate;
+    }
+
+    if( !pcbFile.FileExists() )
+    {
+        wxFileName candidate( prjFile.GetPath(), prjFile.GetName(), wxS( "pcb" ) );
+
+        if( candidate.FileExists() )
+            pcbFile = candidate;
+    }
+
+    if( !pcbFile.FileExists() )
+    {
+        wxFileName candidate( layoutDir.GetPath(), prjFile.GetName(), wxS( "pcb" ) );
+
+        if( candidate.FileExists() )
+            pcbFile = candidate;
+    }
+
+    const wxString pcbWildcard = _( "gEDA / Lepton EDA PCB files" ) + wxS( " (*.pcb)|*.pcb" );
+
+    if( !pcbFile.FileExists() )
+        promptForMissingFile( _( "Locate gEDA / Lepton EDA PCB" ), pcbWildcard, pcbFile );
+
+    if( pcbFile.FileExists() )
+        doImport( pcbFile.GetFullPath(), FRAME_PCB_EDITOR, PCB_IO_MGR::GEDA_PCB );
+}
+
+
 void IMPORT_PROJ_HELPER::ImportFiles( int aImportedSchFileType, int aImportedPcbFileType )
 {
     m_properties.clear();
@@ -345,6 +595,57 @@ void IMPORT_PROJ_HELPER::ImportFiles( int aImportedSchFileType, int aImportedPcb
         AltiumProjectHandler();
         return;
     }
+    else if( aImportedSchFileType == SCH_IO_MGR::SCH_GEDA )
+    {
+        if( m_InputFile.GetExt().CmpNoCase( "prj" ) == 0 )
+        {
+            GedaProjectHandler();
+        }
+        else if( m_InputFile.GetExt().CmpNoCase( "pcb" ) == 0 )
+        {
+            ImportIndividualFile( PCB_T, aImportedPcbFileType );
+        }
+        else
+        {
+            // When importing a bare .sch file, pass the original source directory
+            // so the importer can find symbols in subdirectories relative to the
+            // gEDA / Lepton EDA schematic, even though the file may be copied to a new location
+            // for the KiCad project.
+            wxString sourceDir = m_InputFile.GetPath();
+            wxString symPaths = sourceDir;
+
+            auto discoverSymDirs = [&]( const wxString& aBaseDir )
+            {
+                wxDir dir( aBaseDir );
+
+                if( !dir.IsOpened() )
+                    return;
+
+                wxString subdir;
+                bool     cont = dir.GetFirst( &subdir, wxEmptyString, wxDIR_DIRS );
+
+                while( cont )
+                {
+                    wxString subdirPath =
+                            aBaseDir + wxFileName::GetPathSeparator() + subdir;
+                    wxDir childDir( subdirPath );
+
+                    if( childDir.IsOpened() && childDir.HasFiles( wxT( "*.sym" ) ) )
+                        symPaths += wxT( "\n" ) + subdirPath;
+
+                    cont = dir.GetNext( &subdir );
+                }
+            };
+
+            discoverSymDirs( sourceDir );
+            m_properties["sym_search_paths"] = symPaths.ToStdString();
+
+            doImport( m_InputFile.GetFullPath(), FRAME_SCH, SCH_IO_MGR::SCH_GEDA );
+            ImportIndividualFile( PCB_T, aImportedPcbFileType );
+        }
+
+        return;
+    }
 
     ImportIndividualFile( SCHEMATIC_T, aImportedSchFileType );
     ImportIndividualFile( PCB_T, aImportedPcbFileType );

kicad/import_proj.h

@@ -82,6 +82,8 @@ private:
     void EasyEDAProProjectHandler();
 
     void AltiumProjectHandler();
+
+    void GedaProjectHandler();
 };
 
 #endif

kicad/import_project.cpp

@@ -203,3 +203,11 @@ void KICAD_MANAGER_FRAME::OnImportPadsProjectFiles( wxCommandEvent& event )
                            { "asc", "txt" }, { "asc", "txt" }, SCH_IO_MGR::SCH_PADS,
                            PCB_IO_MGR::PADS );
 }
+
+
+void KICAD_MANAGER_FRAME::OnImportGedaFiles( wxCommandEvent& event )
+{
+    ImportNonKiCadProject( _( "Import gEDA / Lepton EDA Project Files" ),
+                           FILEEXT::GedaProjectFilesWildcard(), { "prj", "sch" }, { "pcb" },
+                           SCH_IO_MGR::SCH_GEDA, PCB_IO_MGR::GEDA_PCB );
+}

kicad/kicad_id.h

@@ -41,7 +41,8 @@ enum id_kicad_frm {
     ID_IMPORT_EASYEDA_PROJECT,
     ID_IMPORT_EASYEDAPRO_PROJECT,
     ID_IMPORT_ALTIUM_PROJECT,
-    ID_IMPORT_PADS_PROJECT
+    ID_IMPORT_PADS_PROJECT,
+    ID_IMPORT_GEDA_PROJECT
 };
 
 #endif

kicad/kicad_manager_frame.cpp

@@ -119,6 +119,7 @@ BEGIN_EVENT_TABLE( KICAD_MANAGER_FRAME, EDA_BASE_FRAME )
     EVT_MENU( ID_IMPORT_EASYEDAPRO_PROJECT, KICAD_MANAGER_FRAME::OnImportEasyEdaProFiles )
     EVT_MENU( ID_IMPORT_ALTIUM_PROJECT, KICAD_MANAGER_FRAME::OnImportAltiumProjectFiles )
     EVT_MENU( ID_IMPORT_PADS_PROJECT, KICAD_MANAGER_FRAME::OnImportPadsProjectFiles )
+    EVT_MENU( ID_IMPORT_GEDA_PROJECT, KICAD_MANAGER_FRAME::OnImportGedaFiles )
 
     // Range menu events
     EVT_MENU_RANGE( ID_FILE1, ID_FILEMAX, KICAD_MANAGER_FRAME::OnFileHistory )

kicad/kicad_manager_frame.h

@@ -130,6 +130,11 @@ public:
      */
     void OnImportPadsProjectFiles( wxCommandEvent& event );
 
+    /**
+     *  Open dialog to import gEDA/gaf schematic and PCB files.
+     */
+    void OnImportGedaFiles( wxCommandEvent& event );
+
     /**
      * Prints the current working directory name and the project name on the text panel.
      */

kicad/menubar.cpp

@@ -149,6 +149,11 @@ void KICAD_MANAGER_FRAME::doReCreateMenuBar()
                      _( "Import PADS Logic schematic and PADS ASCII PCB (*.asc, *.txt)" ),
                      ID_IMPORT_PADS_PROJECT, BITMAPS::import_project );
 
+    importMenu->Add( _( "gEDA / Lepton EDA Project..." ),
+                     _( "Import gEDA or Lepton EDA schematic and PCB layout" ),
+                     ID_IMPORT_GEDA_PROJECT,
+                     BITMAPS::import_project );
+
     fileMenu->Add( importMenu );
 
     fileMenu->AppendSeparator();

pcbnew/files.cpp

@@ -1187,6 +1187,7 @@ bool PCB_EDIT_FRAME::importFile( const wxString& aFileName, int aFileType,
     case PCB_IO_MGR::EAGLE:
     case PCB_IO_MGR::EASYEDA:
     case PCB_IO_MGR::EASYEDAPRO:
+    case PCB_IO_MGR::GEDA_PCB:
         return OpenProjectFiles( std::vector<wxString>( 1, aFileName ), KICTL_NONKICAD_ONLY | KICTL_IMPORT_LIB );
 
     case PCB_IO_MGR::ALTIUM_DESIGNER:

pcbnew/pcb_io/geda/pcb_io_geda.h

@@ -20,41 +20,71 @@
  * or you may search the http://www.gnu.org website for the version 2 license,
  * or you may write to the Free Software Foundation, Inc.,
  * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA
+ *
+ * This file contains file format knowledge derived from the gEDA/pcb project:
+ *
+ *   gEDA/gaf  - Copyright (C) 1998-2010 Ales Hvezda
+ *               Copyright (C) 1998-2016 gEDA Contributors
+ *   Lepton EDA - Copyright (C) 2017-2024 Lepton EDA Contributors
+ *
+ * Both projects are licensed under the GNU General Public License v2 or later.
+ * See https://github.com/lepton-eda/lepton-eda and
+ *     https://github.com/rlutz/geda-gaf
  */
 
 /**
- * @file pcb_io_geda.cpp
+ * @file pcb_io_geda.h
  * @brief Geda PCB file plugin definition file.
  */
 
 #ifndef PCB_IO_GEDA_H_
 #define PCB_IO_GEDA_H_
 
+#include <map>
 #include <string>
+#include <vector>
 
+#include <layer_ids.h>
 #include <pcb_io/pcb_io.h>
 #include <pcb_io/pcb_io_mgr.h>
 
+class BOARD;
+class FOOTPRINT;
 class GPCB_FPL_CACHE;
 class LINE_READER;
+class NETINFO_ITEM;
 
 /**
  * A #PLUGIN derivation for saving and loading Geda PCB files.
  *
  * @note This class is not thread safe, but it is re-entrant multiple times in sequence.
- * @note Currently only reading GPCB footprint files is implemented.
  */
 class PCB_IO_GEDA : public PCB_IO
 {
 public:
+    // Board-level file support
+    const IO_BASE::IO_FILE_DESC GetBoardFileDesc() const override
+    {
+        return IO_BASE::IO_FILE_DESC( _HKI( "gEDA / Lepton EDA PCB board file" ), { "pcb" } );
+    }
+
+    bool CanReadBoard( const wxString& aFileName ) const override;
+
+    BOARD* LoadBoard( const wxString& aFileName, BOARD* aAppendToMe,
+                      const std::map<std::string, UTF8>* aProperties = nullptr,
+                      PROJECT* aProject = nullptr ) override;
+
+    std::vector<FOOTPRINT*> GetImportedCachedLibraryFootprints() override;
+
+    // Footprint library support
     const IO_BASE::IO_FILE_DESC GetLibraryFileDesc() const override
     {
-        return IO_BASE::IO_FILE_DESC( _HKI( "gEDA PCB footprint file" ), { "fp" } );
+        return IO_BASE::IO_FILE_DESC( _HKI( "gEDA / Lepton EDA PCB footprint file" ), { "fp" } );
     }
 
     const IO_BASE::IO_FILE_DESC GetLibraryDesc() const override
     {
-        return IO_BASE::IO_FILE_DESC( _HKI( "gEDA PCB footprint library directory" ), {}, { "fp" },
+        return IO_BASE::IO_FILE_DESC( _HKI( "gEDA / Lepton EDA PCB footprint library directory" ), {}, { "fp" },
                                       false );
     }
 
@@ -85,7 +115,7 @@ public:
 
     PCB_IO_GEDA( int aControlFlags );
 
-    ~PCB_IO_GEDA();
+    ~PCB_IO_GEDA() override;
 
 private:
     void validateCache( const wxString& aLibraryPath, bool checkModified = true );
@@ -97,12 +127,28 @@ private:
 
     friend class GPCB_FPL_CACHE;
 
+    // Board parsing helpers
+    PCB_LAYER_ID mapLayer( int aGedaLayer, const wxString& aLayerName ) const;
+
+    void parseVia( wxArrayString& aParameters, double aConvUnit );
+    FOOTPRINT* parseElement( wxArrayString& aParameters, LINE_READER* aLineReader,
+                             double aConvUnit );
+    void parseLayer( wxArrayString& aParameters, LINE_READER* aLineReader, double aConvUnit );
+    void parseNetList( LINE_READER* aLineReader );
+    void parseParameters( wxArrayString& aParameterList, LINE_READER* aLineReader );
+    bool testFlags( const wxString& aFlag, long aMask, const wxChar* aName );
+
 protected:
     wxString               m_error;    ///< for throwing exceptions
     GPCB_FPL_CACHE*        m_cache;    ///< Footprint library cache.
     int                    m_ctl;
     LINE_READER*           m_reader;   ///< no ownership here.
     wxString               m_filename; ///< for saves only, name is in m_reader for loads
+
+    // Board import state
+    std::vector<FOOTPRINT*>                     m_cachedFootprints;
+    std::map<wxString, NETINFO_ITEM*>           m_netMap;
+    int                                         m_numCopperLayers;
 };
 
 #endif  // PCB_IO_GEDA_H_

pcbnew/pcb_io/pcb_io_mgr.cpp

@@ -329,7 +329,7 @@ static PCB_IO_MGR::REGISTER_PLUGIN registerFabmasterPlugin(
 
 static PCB_IO_MGR::REGISTER_PLUGIN registerGPCBPlugin(
         PCB_IO_MGR::GEDA_PCB,
-        wxT( "GEDA/Pcb" ),
+        wxT( "gEDA / Lepton EDA" ),
         []() -> PCB_IO* { return new PCB_IO_GEDA; } );
 
 static PCB_IO_MGR::REGISTER_PLUGIN registerPcadPlugin(

qa/data/eeschema/io/geda/7400-1.sym

@@ -0,0 +1,37 @@
+v 20130925 2
+T 300 300 8 10 0 0 0 0 1
+device=7400
+P 0 200 200 200 1 0 0
+{
+T 50 250 5 8 0 1 0 0 1
+pinnumber=1
+T 50 250 5 8 0 0 0 0 1
+pinseq=1
+T 50 250 5 8 0 1 0 0 1
+pinlabel=A
+T 50 250 5 8 0 1 0 0 1
+pintype=in
+}
+P 0 0 200 0 1 0 0
+{
+T 50 50 5 8 0 1 0 0 1
+pinnumber=2
+T 50 50 5 8 0 0 0 0 1
+pinseq=2
+T 50 50 5 8 0 1 0 0 1
+pinlabel=B
+T 50 50 5 8 0 1 0 0 1
+pintype=in
+}
+P 500 100 300 100 1 0 0
+{
+T 350 150 5 8 0 1 0 0 1
+pinnumber=3
+T 350 150 5 8 0 0 0 0 1
+pinseq=3
+T 350 150 5 8 0 1 0 0 1
+pinlabel=Y
+T 350 150 5 8 0 1 0 0 1
+pintype=out
+}
+B 200 -100 100 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

qa/data/eeschema/io/geda/ayab/gafrc

@@ -0,0 +1,2 @@
+(component-library "gschem-symbols")
+(component-library "stdlib")

qa/data/eeschema/io/geda/ayab/gschem-symbols/MetroMini.sym

@@ -0,0 +1,321 @@
+v 20130925 2
+L 300 0 1700 0 3 0 0 0 -1 -1
+L 300 4400 300 0 3 0 0 0 -1 -1
+L 300 4400 1700 4400 3 0 0 0 -1 -1
+L 1700 4400 1700 0 3 0 0 0 -1 -1
+P 0 4100 300 4100 1 0 0
+{
+T 0 4100 5 10 0 0 0 0 1
+pintype=io
+T 355 4095 9 8 1 1 0 0 1
+pinlabel=VUSB
+T 205 4145 5 8 1 1 0 6 1
+pinnumber=1
+T 0 4100 5 10 0 0 0 0 1
+pinseq=1
+}
+P 0 3800 300 3800 1 0 0
+{
+T 0 3800 5 10 0 0 0 0 1
+pintype=io
+T 355 3795 9 8 1 1 0 0 1
+pinlabel=RST
+T 205 3845 5 8 1 1 0 6 1
+pinnumber=2
+T 0 3800 5 10 0 0 0 0 1
+pinseq=2
+}
+P 0 3500 300 3500 1 0 0
+{
+T 0 3500 5 10 0 0 0 0 1
+pintype=io
+T 355 3495 9 8 1 1 0 0 1
+pinlabel=3V
+T 205 3545 5 8 1 1 0 6 1
+pinnumber=3
+T 0 3500 5 10 0 0 0 0 1
+pinseq=3
+}
+P 0 3200 300 3200 1 0 0
+{
+T 0 3200 5 10 0 0 0 0 1
+pintype=io
+T 355 3195 9 8 1 1 0 0 1
+pinlabel=5V
+T 205 3245 5 8 1 1 0 6 1
+pinnumber=4
+T 0 3200 5 10 0 0 0 0 1
+pinseq=4
+}
+P 0 2900 300 2900 1 0 0
+{
+T 0 2900 5 10 0 0 0 0 1
+pintype=io
+T 355 2895 9 8 1 1 0 0 1
+pinlabel=GND
+T 205 2945 5 8 1 1 0 6 1
+pinnumber=5
+T 0 2900 5 10 0 0 0 0 1
+pinseq=5
+}
+P 0 2600 300 2600 1 0 0
+{
+T 0 2600 5 10 0 0 0 0 1
+pintype=io
+T 355 2595 9 8 1 1 0 0 1
+pinlabel=GND
+T 205 2645 5 8 1 1 0 6 1
+pinnumber=6
+T 0 2600 5 10 0 0 0 0 1
+pinseq=6
+}
+P 0 2300 300 2300 1 0 0
+{
+T 0 2300 5 10 0 0 0 0 1
+pintype=io
+T 355 2295 9 8 1 1 0 0 1
+pinlabel=VIN
+T 205 2345 5 8 1 1 0 6 1
+pinnumber=7
+T 0 2300 5 10 0 0 0 0 1
+pinseq=7
+}
+P 0 2000 300 2000 1 0 0
+{
+T 0 2000 5 10 0 0 0 0 1
+pintype=io
+T 355 1995 9 8 1 1 0 0 1
+pinlabel=AREF
+T 205 2045 5 8 1 1 0 6 1
+pinnumber=8
+T 0 2000 5 10 0 0 0 0 1
+pinseq=8
+}
+P 0 1700 300 1700 1 0 0
+{
+T 0 1700 5 10 0 0 0 0 1
+pintype=io
+T 355 1695 9 8 1 1 0 0 1
+pinlabel=A0
+T 205 1745 5 8 1 1 0 6 1
+pinnumber=9
+T 0 1700 5 10 0 0 0 0 1
+pinseq=9
+}
+P 0 1400 300 1400 1 0 0
+{
+T 0 1400 5 10 0 0 0 0 1
+pintype=io
+T 355 1395 9 8 1 1 0 0 1
+pinlabel=A1
+T 205 1445 5 8 1 1 0 6 1
+pinnumber=10
+T 0 1400 5 10 0 0 0 0 1
+pinseq=10
+}
+P 0 1100 300 1100 1 0 0
+{
+T 0 1100 5 10 0 0 0 0 1
+pintype=io
+T 355 1095 9 8 1 1 0 0 1
+pinlabel=A2
+T 205 1145 5 8 1 1 0 6 1
+pinnumber=11
+T 0 1100 5 10 0 0 0 0 1
+pinseq=11
+}
+P 0 800 300 800 1 0 0
+{
+T 0 800 5 10 0 0 0 0 1
+pintype=io
+T 355 795 9 8 1 1 0 0 1
+pinlabel=A3
+T 205 845 5 8 1 1 0 6 1
+pinnumber=12
+T 0 800 5 10 0 0 0 0 1
+pinseq=12
+}
+P 0 500 300 500 1 0 0
+{
+T 0 500 5 10 0 0 0 0 1
+pintype=io
+T 355 495 9 8 1 1 0 0 1
+pinlabel=A4
+T 205 545 5 8 1 1 0 6 1
+pinnumber=13
+T 0 500 5 10 0 0 0 0 1
+pinseq=13
+}
+P 0 200 300 200 1 0 0
+{
+T 0 200 5 10 0 0 0 0 1
+pintype=io
+T 355 195 9 8 1 1 0 0 1
+pinlabel=A5
+T 205 245 5 8 1 1 0 6 1
+pinnumber=14
+T 0 200 5 10 0 0 0 0 1
+pinseq=14
+}
+P 2000 200 1700 200 1 0 0
+{
+T 2000 200 5 10 0 0 0 0 1
+pintype=io
+T 1645 195 9 8 1 1 0 6 1
+pinlabel=D0
+T 1795 245 5 8 1 1 0 0 1
+pinnumber=15
+T 2000 200 5 10 0 0 0 0 1
+pinseq=15
+}
+P 2000 500 1700 500 1 0 0
+{
+T 2000 500 5 10 0 0 0 0 1
+pintype=io
+T 1645 495 9 8 1 1 0 6 1
+pinlabel=D1
+T 1795 545 5 8 1 1 0 0 1
+pinnumber=16
+T 2000 500 5 10 0 0 0 0 1
+pinseq=16
+}
+P 2000 800 1700 800 1 0 0
+{
+T 2000 800 5 10 0 0 0 0 1
+pintype=io
+T 1645 795 9 8 1 1 0 6 1
+pinlabel=D2
+T 1795 845 5 8 1 1 0 0 1
+pinnumber=17
+T 2000 800 5 10 0 0 0 0 1
+pinseq=17
+}
+P 2000 1100 1700 1100 1 0 0
+{
+T 2000 1100 5 10 0 0 0 0 1
+pintype=io
+T 1645 1095 9 8 1 1 0 6 1
+pinlabel=D3
+T 1795 1145 5 8 1 1 0 0 1
+pinnumber=18
+T 2000 1100 5 10 0 0 0 0 1
+pinseq=18
+}
+P 2000 1400 1700 1400 1 0 0
+{
+T 2000 1400 5 10 0 0 0 0 1
+pintype=io
+T 1645 1395 9 8 1 1 0 6 1
+pinlabel=D4
+T 1795 1445 5 8 1 1 0 0 1
+pinnumber=19
+T 2000 1400 5 10 0 0 0 0 1
+pinseq=19
+}
+P 2000 1700 1700 1700 1 0 0
+{
+T 2000 1700 5 10 0 0 0 0 1
+pintype=io
+T 1645 1695 9 8 1 1 0 6 1
+pinlabel=D5
+T 1795 1745 5 8 1 1 0 0 1
+pinnumber=20
+T 2000 1700 5 10 0 0 0 0 1
+pinseq=20
+}
+P 2000 2000 1700 2000 1 0 0
+{
+T 2000 2000 5 10 0 0 0 0 1
+pintype=io
+T 1645 1995 9 8 1 1 0 6 1
+pinlabel=D6
+T 1795 2045 5 8 1 1 0 0 1
+pinnumber=21
+T 2000 2000 5 10 0 0 0 0 1
+pinseq=21
+}
+P 2000 2300 1700 2300 1 0 0
+{
+T 2000 2300 5 10 0 0 0 0 1
+pintype=io
+T 1645 2295 9 8 1 1 0 6 1
+pinlabel=D7
+T 1795 2345 5 8 1 1 0 0 1
+pinnumber=22
+T 2000 2300 5 10 0 0 0 0 1
+pinseq=22
+}
+P 2000 2600 1700 2600 1 0 0
+{
+T 2000 2600 5 10 0 0 0 0 1
+pintype=io
+T 1645 2595 9 8 1 1 0 6 1
+pinlabel=D8
+T 1795 2645 5 8 1 1 0 0 1
+pinnumber=23
+T 2000 2600 5 10 0 0 0 0 1
+pinseq=23
+}
+P 2000 2900 1700 2900 1 0 0
+{
+T 2000 2900 5 10 0 0 0 0 1
+pintype=io
+T 1645 2895 9 8 1 1 0 6 1
+pinlabel=D9
+T 1795 2945 5 8 1 1 0 0 1
+pinnumber=24
+T 2000 2900 5 10 0 0 0 0 1
+pinseq=24
+}
+P 2000 3200 1700 3200 1 0 0
+{
+T 2000 3200 5 10 0 0 0 0 1
+pintype=io
+T 1645 3195 9 8 1 1 0 6 1
+pinlabel=D10
+T 1795 3245 5 8 1 1 0 0 1
+pinnumber=25
+T 2000 3200 5 10 0 0 0 0 1
+pinseq=25
+}
+P 2000 3500 1700 3500 1 0 0
+{
+T 2000 3500 5 10 0 0 0 0 1
+pintype=io
+T 1645 3495 9 8 1 1 0 6 1
+pinlabel=D11
+T 1795 3545 5 8 1 1 0 0 1
+pinnumber=26
+T 2000 3500 5 10 0 0 0 0 1
+pinseq=26
+}
+P 2000 3800 1700 3800 1 0 0
+{
+T 2000 3800 5 10 0 0 0 0 1
+pintype=io
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qa/data/eeschema/io/geda/ayab/gschem-symbols/PCF8574T-2.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/ULN2803A.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/beeper.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/connector10-1B.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/connector14-1.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/connector3-1B.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/connector4-1B.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/connector5-1B.sym

@@ -0,0 +1,66 @@
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qa/data/eeschema/io/geda/ayab/gschem-symbols/connector8-1B.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/diode-3a.sym

@@ -0,0 +1,33 @@
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qa/data/eeschema/io/geda/ayab/gschem-symbols/led-small.sym

@@ -0,0 +1,39 @@
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qa/data/eeschema/io/geda/ayab/gschem-symbols/nc-x.sym

@@ -0,0 +1,18 @@
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qa/data/eeschema/io/geda/ayab/gschem-symbols/resistorpack8-isolated2.sym

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qa/data/eeschema/io/geda/ayab/gschem-symbols/switch-tact_sq.sym

@@ -0,0 +1,64 @@
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qa/data/eeschema/io/geda/ayab/gschem-symbols/trans_BEC_NPN.sym

@@ -0,0 +1,47 @@
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qa/data/eeschema/io/geda/ayab/stdlib/capacitor-1.sym

@@ -0,0 +1,31 @@
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qa/data/eeschema/io/geda/ayab/stdlib/capacitor-2.sym

@@ -0,0 +1,31 @@
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qa/data/eeschema/io/geda/ayab/stdlib/generic-power.sym

@@ -0,0 +1,15 @@
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qa/data/eeschema/io/geda/ayab/stdlib/gnd-1.sym

@@ -0,0 +1,17 @@
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qa/data/eeschema/io/geda/ayab/stdlib/input-1.sym

@@ -0,0 +1,17 @@
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qa/data/eeschema/io/geda/ayab/stdlib/nc-right-1.sym

@@ -0,0 +1,16 @@
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qa/data/eeschema/io/geda/ayab/stdlib/output-1.sym

@@ -0,0 +1,17 @@
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+pinseq=1
+T 50 250 5 8 0 1 0 0 1
+pinlabel=1
+T 50 250 5 8 0 1 0 0 1
+pintype=in
+}
+L 200 400 200 0 3 0 0 0 -1 -1
+L 200 400 500 200 3 0 0 0 -1 -1
+L 200 0 500 200 3 0 0 0 -1 -1

qa/data/eeschema/io/geda/ayab/stdlib/resistor-1.sym

@@ -0,0 +1,28 @@
+v 20130925 2
+T 300 400 8 10 1 1 0 0 1
+refdes=R?
+T 300 -100 8 10 0 0 0 0 1
+device=RESISTOR
+P 0 200 200 200 1 0 0
+{
+T 100 250 5 8 0 1 0 0 1
+pinnumber=2
+T 100 250 5 8 0 0 0 0 1
+pinseq=2
+T 100 250 5 8 0 1 0 0 1
+pinlabel=2
+T 100 250 5 8 0 1 0 0 1
+pintype=pas
+}
+P 900 200 700 200 1 0 0
+{
+T 800 250 5 8 0 1 0 0 1
+pinnumber=1
+T 800 250 5 8 0 0 0 0 1
+pinseq=1
+T 800 250 5 8 0 1 0 0 1
+pinlabel=1
+T 800 250 5 8 0 1 0 0 1
+pintype=pas
+}
+B 200 100 500 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

qa/data/eeschema/io/geda/ayab/stdlib/terminal-1.sym

@@ -0,0 +1,17 @@
+v 20130925 2
+T 300 500 8 10 0 0 0 0 1
+device=terminal
+T 100 600 8 10 1 1 0 0 1
+refdes=T?
+P 200 200 0 200 1 0 0
+{
+T 50 250 5 8 0 1 0 0 1
+pinnumber=1
+T 50 250 5 8 0 0 0 0 1
+pinseq=1
+T 50 250 5 8 0 1 0 0 1
+pinlabel=1
+T 50 250 5 8 0 1 0 0 1
+pintype=pas
+}
+B 200 100 200 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

qa/data/eeschema/io/geda/ayab/stdlib/title-D.sym

@@ -0,0 +1,4 @@
+v 20130925 2
+T 0 0 8 10 0 0 0 0 1
+device=TITLEBLOCK
+B 0 0 34000 22000 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

qa/data/eeschema/io/geda/bezier_test.sch

@@ -0,0 +1,8 @@
+v 20130925 2
+H 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 2
+M 100,100
+C 200,200 300,200 400,100
+H 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 3
+M 500,500
+C 600,700 800,700 900,500
+L 900,300

qa/data/eeschema/io/geda/bus_ripper_test.sch

@@ -0,0 +1,4 @@
+v 20130925 2
+U 40000 45000 40000 50000 10 1
+N 40000 47000 38000 47000 4
+N 40000 49000 38000 49000 4

qa/data/eeschema/io/geda/bus_test.sch

@@ -0,0 +1,4 @@
+v 20130925 2
+U 40000 45000 50000 45000 10 0
+U 50000 45000 50000 40000 10 0
+N 40000 45000 38000 45000 4

qa/data/eeschema/io/geda/comments_test.sch

@@ -0,0 +1,12 @@
+v 20130925 2
+# This is a comment line that should be ignored
+C 44000 47000 1 0 0 resistor-1.sym
+{
+T 44300 47400 5 10 1 1 0 0 1
+refdes=R1
+# Another comment inside an attribute block area
+T 44300 46700 5 10 1 1 0 0 1
+value=1k
+}
+# Comment between objects
+N 44000 47100 43000 47100 4

qa/data/eeschema/io/geda/documentation_test.sch

@@ -0,0 +1,10 @@
+v 20130925 2
+C 44000 47000 1 0 0 resistor-1.sym
+{
+T 44300 47400 5 10 1 1 0 0 1
+refdes=R1
+T 44300 46700 5 10 1 1 0 0 1
+value=10k
+T 44300 48000 5 10 0 0 0 0 1
+documentation=http://www.example.com/datasheet.pdf
+}

qa/data/eeschema/io/geda/embedded_prefix_test.sch

@@ -0,0 +1,29 @@
+v 20130925 2
+C 1000 1000 1 0 0 EMBEDDEDresistor-1.sym
+{
+T 1200 1800 5 10 1 1 0 0 1
+refdes=R1
+T 1200 1600 5 10 0 1 0 0 1
+value=10k
+}
+[
+P 0 200 200 200 1 0 0
+{
+T 100 300 5 8 0 1 0 0 1
+pinnumber=1
+T 100 300 5 8 0 1 0 0 1
+pinlabel=1
+}
+L 200 300 200 100 3 0 0 0 -1 -1
+L 200 300 800 200 3 0 0 0 -1 -1
+L 800 200 200 100 3 0 0 0 -1 -1
+P 1000 200 800 200 1 0 0
+{
+T 900 300 5 8 0 1 0 0 1
+pinnumber=2
+T 900 300 5 8 0 1 0 0 1
+pinlabel=2
+}
+T 500 0 8 10 0 0 0 0 1
+device=RESISTOR
+]

qa/data/eeschema/io/geda/extra-syms/props_resistor.sym

@@ -0,0 +1,28 @@
+v 20130925 2
+B 200 0 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 300 500 5 10 0 0 0 0 1
+device=RESISTOR
+P 900 200 700 200 1 0 0
+{
+T 700 250 5 8 0 1 0 0 1
+pinnumber=2
+T 700 250 5 8 0 0 0 0 1
+pinseq=2
+T 700 250 5 8 0 1 0 0 1
+pinlabel=2
+T 700 250 5 8 0 1 0 0 1
+pintype=pas
+}
+P 0 200 200 200 1 0 0
+{
+T 100 250 5 8 0 1 0 0 1
+pinnumber=1
+T 100 250 5 8 0 0 0 0 1
+pinseq=1
+T 100 250 5 8 0 1 0 0 1
+pinlabel=1
+T 100 250 5 8 0 1 0 0 1
+pintype=pas
+}
+T 200 500 8 10 1 1 0 0 1
+refdes=R?

qa/data/eeschema/io/geda/fuzzy_match_test.sch

@@ -0,0 +1,9 @@
+v 20130925 2
+C 44000 47000 1 0 0 resistor-11.sym
+{
+T 44300 47400 5 10 1 1 0 0 1
+refdes=R1
+T 44300 46700 5 10 1 1 0 0 1
+value=10k
+}
+N 44000 47000 43000 47000 4

qa/data/eeschema/io/geda/goodfet50.sch

@@ -0,0 +1,476 @@
+v 20110115 2
+C 40000 40000 0 0 0 title-B.sym
+C 45400 42400 1 0 0 msp430f550x-1.sym
+{
+T 49600 50000 5 10 1 1 0 6 1
+refdes=U3
+T 45700 50200 5 10 0 0 0 0 1
+device=MSP430F550x
+T 45700 50400 5 10 0 0 0 0 1
+footprint=LQFP48_7
+}
+C 40200 48700 1 0 0 micro-usb.sym
+{
+T 42000 50700 5 10 1 1 0 6 1
+refdes=U1
+T 40600 50900 5 10 0 0 0 0 1
+device=MICRO_B
+T 40500 48900 5 10 1 1 0 0 1
+footprint=USB_MICRO_B
+}
+N 42300 50300 43300 50300 4
+{
+T 42400 50300 5 10 1 1 0 0 1
+netname=+5V
+}
+N 42300 50000 43300 50000 4
+{
+T 42400 50000 5 10 1 1 0 0 1
+netname=USBDM
+}
+N 43300 49700 42300 49700 4
+{
+T 42400 49700 5 10 1 1 0 0 1
+netname=USBDP
+}
+N 43300 49100 42300 49100 4
+{
+T 42400 49100 5 10 1 1 0 0 1
+netname=GND
+}
+N 45400 47800 43600 47800 4
+{
+T 44500 47800 5 10 1 1 0 0 1
+netname=+3V3
+}
+N 44500 46600 45400 46600 4
+{
+T 44600 46600 5 10 1 1 0 0 1
+netname=+3V3
+}
+C 43700 46400 1 90 0 capacitor-1.sym
+{
+T 43000 46600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 43200 46600 5 10 1 1 90 0 1
+refdes=C3
+T 42800 46600 5 10 0 0 90 0 1
+symversion=0.1
+T 43900 46600 5 10 1 1 90 0 1
+value=0.1uF
+T 43700 46400 5 10 1 1 0 0 1
+footprint=0603
+}
+N 43500 46300 45400 46300 4
+{
+T 44600 46300 5 10 1 1 0 0 1
+netname=GND
+}
+N 44500 46600 44500 47400 4
+N 44500 47400 43500 47400 4
+N 43600 46000 45400 46000 4
+N 43600 45400 45400 45400 4
+{
+T 44500 45400 5 10 1 1 0 0 1
+netname=P1.1
+}
+N 43600 45100 45400 45100 4
+{
+T 44500 45100 5 10 1 1 0 0 1
+netname=P1.2
+}
+N 43600 44800 45400 44800 4
+{
+T 44500 44800 5 10 1 1 0 0 1
+netname=P1.3
+}
+N 49900 43300 50700 43300 4
+{
+T 50000 43300 5 10 1 1 0 0 1
+netname=GND
+}
+N 49900 43600 50700 43600 4
+{
+T 50000 43600 5 10 1 1 0 0 1
+netname=+3V3
+}
+N 51200 43900 49900 43900 4
+{
+T 50000 43900 5 10 1 1 0 0 1
+netname=SCLK1
+}
+N 51200 45100 49900 45100 4
+{
+T 50000 45100 5 10 1 1 0 0 1
+netname=TXD1
+}
+N 49900 45400 51200 45400 4
+{
+T 50000 45400 5 10 1 1 0 0 1
+netname=RXD1
+}
+N 49900 49300 51200 49300 4
+N 51200 49600 49900 49600 4
+N 49900 46300 50700 46300 4
+{
+T 50100 46300 5 10 1 1 0 0 1
+netname=GND
+}
+N 49900 48400 51000 48400 4
+{
+T 50100 48400 5 10 1 1 0 0 1
+netname=GND
+}
+N 49900 47800 50700 47800 4
+{
+T 50100 47800 5 10 1 1 0 0 1
+netname=+3V3
+}
+N 49900 47500 50700 47500 4
+{
+T 50100 47500 5 10 1 1 0 0 1
+netname=+5V
+}
+N 49900 47200 50700 47200 4
+{
+T 50000 47200 5 10 1 1 0 0 1
+netname=USBDM
+}
+N 50700 46600 49900 46600 4
+{
+T 50000 46600 5 10 1 1 0 0 1
+netname=USBDP
+}
+N 49900 46900 50700 46900 4
+{
+T 50000 46900 5 10 1 1 0 0 1
+netname=PUR
+}
+N 49900 48100 51000 48100 4
+N 49900 48700 50700 48700 4
+{
+T 50100 48700 5 10 1 1 0 0 1
+netname=XTI
+}
+N 49900 49000 50700 49000 4
+{
+T 50100 49000 5 10 1 1 0 0 1
+netname=XTO
+}
+C 51500 47800 1 90 0 capacitor-1.sym
+{
+T 50800 48000 5 10 0 0 90 0 1
+device=CAPACITOR
+T 51000 48000 5 10 1 1 90 0 1
+refdes=C6
+T 50600 48000 5 10 0 0 90 0 1
+symversion=0.1
+T 51700 48000 5 10 1 1 90 0 1
+value=0.1uF
+T 51500 47800 5 10 1 1 0 0 1
+footprint=0603
+}
+N 51000 48400 51000 48700 4
+N 51000 48700 51300 48700 4
+N 51300 47800 51000 47800 4
+N 51000 47800 51000 48100 4
+C 41400 41200 1 0 0 capacitor-1.sym
+{
+T 41600 41900 5 10 0 0 0 0 1
+device=CAPACITOR
+T 41600 41700 5 10 1 1 0 0 1
+refdes=C5
+T 41600 42100 5 10 0 0 0 0 1
+symversion=0.1
+T 41600 41000 5 10 1 1 0 0 1
+value=0.1uF
+T 41400 41200 5 10 1 1 0 0 1
+footprint=0603
+}
+N 42300 41400 43300 41400 4
+{
+T 42400 41400 5 10 1 1 0 0 1
+netname=+5V
+}
+N 41400 41400 40400 41400 4
+{
+T 40500 41400 5 10 1 1 0 0 1
+netname=GND
+}
+C 41400 40500 1 0 0 resistor-1.sym
+{
+T 41700 40900 5 10 0 0 0 0 1
+device=RESISTOR
+T 41600 40800 5 10 1 1 0 0 1
+refdes=R1
+T 41600 40300 5 10 1 1 0 0 1
+value=1k
+T 41400 40500 5 10 1 1 0 0 1
+footprint=0603
+}
+N 41400 40600 40400 40600 4
+{
+T 40500 40600 5 10 1 1 0 0 1
+netname=USBDP
+}
+N 43300 40600 42300 40600 4
+{
+T 42400 40600 5 10 1 1 0 0 1
+netname=+3V3
+}
+N 40200 43900 41700 43900 4
+{
+T 40400 43900 5 10 1 1 0 0 1
+netname=XTO
+}
+N 42400 43900 43700 43900 4
+{
+T 43300 43900 5 10 1 1 0 0 1
+netname=XTI
+}
+N 42100 42300 42100 43200 4
+{
+T 42100 42400 5 10 1 1 90 0 1
+netname=GND
+}
+C 50700 50300 1 0 0 capacitor-1.sym
+{
+T 50900 51000 5 10 0 0 0 0 1
+device=CAPACITOR
+T 50900 50800 5 10 1 1 0 0 1
+refdes=C4
+T 50900 51200 5 10 0 0 0 0 1
+symversion=0.1
+T 50900 50100 5 10 1 1 0 0 1
+value=0.1uF
+T 50700 50300 5 10 1 1 0 0 1
+footprint=0603
+}
+N 49900 50500 50700 50500 4
+{
+T 50100 50500 5 10 1 1 0 0 1
+netname=+3V3
+}
+N 51600 50500 52400 50500 4
+{
+T 51800 50500 5 10 1 1 0 0 1
+netname=GND
+}
+N 45400 46900 45300 46900 4
+N 45300 46900 45300 46300 4
+C 47100 41600 1 0 0 led-2.sym
+{
+T 47900 41900 5 10 1 1 0 0 1
+refdes=D1
+T 47200 42200 5 10 0 0 0 0 1
+device=LED
+T 47100 41600 5 10 1 1 0 0 1
+footprint=0603
+}
+C 47100 41200 1 0 0 led-2.sym
+{
+T 47900 41500 5 10 1 1 0 0 1
+refdes=D2
+T 47200 41800 5 10 0 0 0 0 1
+device=LED
+T 47100 41200 5 10 1 1 0 0 1
+footprint=0603
+}
+C 47100 40800 1 0 0 led-2.sym
+{
+T 47900 41100 5 10 1 1 0 0 1
+refdes=D3
+T 47200 41400 5 10 0 0 0 0 1
+device=LED
+T 47100 40800 5 10 1 1 0 0 1
+footprint=0603
+}
+N 48000 41700 48400 41700 4
+N 48400 41700 48400 40500 4
+N 48400 40500 48000 40500 4
+N 48000 40900 48400 40900 4
+N 48000 41300 48400 41300 4
+N 47100 40900 46000 40900 4
+{
+T 46100 40900 5 10 1 1 0 0 1
+netname=P1.3
+}
+N 47100 41300 46000 41300 4
+{
+T 46100 41300 5 10 1 1 0 0 1
+netname=P1.2
+}
+N 47100 41700 46000 41700 4
+{
+T 46100 41700 5 10 1 1 0 0 1
+netname=P1.1
+}
+N 47100 40500 46000 40500 4
+{
+T 46100 40500 5 10 1 1 0 0 1
+netname=GND
+}
+C 47100 40400 1 0 0 resistor-1.sym
+{
+T 47400 40800 5 10 0 0 0 0 1
+device=RESISTOR
+T 47300 40700 5 10 1 1 0 0 1
+refdes=R2
+T 47300 40200 5 10 1 1 0 0 1
+value=330
+T 47100 40400 5 10 1 1 0 0 1
+footprint=0603
+}
+C 41700 43800 1 0 0 crystal-1.sym
+{
+T 41900 44300 5 10 0 0 0 0 1
+device=CRYSTAL
+T 41900 44100 5 10 1 1 0 0 1
+refdes=X1
+T 41900 44500 5 10 0 0 0 0 1
+symversion=0.1
+T 41700 43800 5 10 0 1 0 0 1
+footprint=HC49
+}
+C 41100 43000 1 0 0 capacitor-1.sym
+{
+T 41300 43700 5 10 0 0 0 0 1
+device=CAPACITOR
+T 41300 43500 5 10 1 1 0 0 1
+refdes=C1
+T 41300 43900 5 10 0 0 0 0 1
+symversion=0.1
+T 41300 42800 5 10 1 1 0 0 1
+value=22pF
+T 41100 43000 5 10 1 1 0 0 1
+footprint=0603
+}
+C 42200 43000 1 0 0 capacitor-1.sym
+{
+T 42400 43700 5 10 0 0 0 0 1
+device=CAPACITOR
+T 42400 43500 5 10 1 1 0 0 1
+refdes=C2
+T 42400 43900 5 10 0 0 0 0 1
+symversion=0.1
+T 42400 42800 5 10 1 1 0 0 1
+value=22pF
+T 42200 43000 5 10 1 1 0 0 1
+footprint=0603
+}
+N 41100 43200 41100 43900 4
+N 43100 43200 43100 43900 4
+N 42200 43200 42000 43200 4
+T 52900 41000 9 20 1 0 0 4 1
+GoodFET 50
+T 54000 40100 9 8 1 0 0 0 1
+TheQUUX!
+T 54000 40400 9 8 1 0 0 0 1
+C
+C 53500 44800 1 0 0 header14-1.sym
+{
+T 54100 47700 5 10 1 1 0 0 1
+refdes=J1
+T 56700 47200 5 10 0 0 0 0 1
+device=HEADER14
+T 53500 44800 5 10 1 0 0 0 1
+footprint=14.fp
+}
+N 54900 47000 56300 47000 4
+{
+T 55500 47000 5 10 1 1 0 0 1
+netname=+3V3
+}
+N 54900 47400 55300 47400 4
+N 52300 45800 53500 45800 4
+{
+T 52400 45800 5 10 1 1 0 0 1
+netname=GND
+}
+N 55300 47400 55300 47000 4
+N 53500 47400 52300 47400 4
+{
+T 52400 47400 5 10 1 1 0 0 1
+netname=TDO
+}
+N 53500 47000 52300 47000 4
+{
+T 52400 47000 5 10 1 1 0 0 1
+netname=TDI
+}
+N 53500 46600 52300 46600 4
+{
+T 52400 46600 5 10 1 1 0 0 1
+netname=TMS
+}
+N 53500 46200 52300 46200 4
+{
+T 52400 46200 5 10 1 1 0 0 1
+netname=TCK
+}
+N 53500 45400 52300 45400 4
+{
+T 52400 45400 5 10 1 1 0 0 1
+netname=RST
+}
+N 54900 45400 56100 45400 4
+{
+T 55100 45400 5 10 1 1 0 0 1
+netname=RXD1
+}
+N 54900 45000 56100 45000 4
+{
+T 55100 45000 5 10 1 1 0 0 1
+netname=TXD1
+}
+N 54900 46200 56100 46200 4
+{
+T 55100 46200 5 10 1 1 0 0 1
+netname=TEST
+}
+N 56100 45800 54900 45800 4
+{
+T 55100 45800 5 10 1 1 0 0 1
+netname=SCLK1
+}
+N 43500 46300 43500 46400 4
+N 43500 47300 43500 47400 4
+N 45400 43000 44200 43000 4
+{
+T 44300 43000 5 10 1 1 0 0 1
+netname=TDO
+}
+N 45400 42700 44200 42700 4
+{
+T 44300 42700 5 10 1 1 0 0 1
+netname=TDI
+}
+N 51100 42700 49900 42700 4
+{
+T 50000 42700 5 10 1 1 0 0 1
+netname=TMS
+}
+N 51100 43000 49900 43000 4
+{
+T 50000 43000 5 10 1 1 0 0 1
+netname=TCK
+}
+N 45400 43300 44200 43300 4
+{
+T 44300 43300 5 10 1 1 0 0 1
+netname=RST
+}
+N 49900 44200 51100 44200 4
+{
+T 50100 44200 5 10 1 1 0 0 1
+netname=TEST
+}
+C 52900 49800 1 180 0 connector2-1.sym
+{
+T 52700 48800 5 10 0 0 180 0 1
+device=CONNECTOR_2
+T 52900 49000 5 10 1 1 180 0 1
+refdes=SBW
+T 52900 49800 5 10 1 0 0 0 1
+footprint=HEADER2_1
+}

qa/data/eeschema/io/geda/graphical_attr_test.sch

@@ -0,0 +1,17 @@
+v 20130925 2
+C 44000 47000 1 0 0 resistor-1.sym
+{
+T 44300 47400 5 10 1 1 0 0 1
+refdes=R1
+T 44300 46700 5 10 1 1 0 0 1
+value=10k
+}
+C 44000 44000 1 0 0 resistor-1.sym
+{
+T 44300 44400 5 10 1 1 0 0 1
+refdes=R2
+T 44300 43700 5 10 1 1 0 0 1
+value=20k
+T 44300 43500 5 10 0 0 0 0 1
+graphical=1
+}

qa/data/eeschema/io/geda/graphical_test.sch

@@ -0,0 +1,16 @@
+v 20130925 2
+C 44000 47000 1 0 0 resistor-1.sym
+{
+T 44300 47400 5 10 1 1 0 0 1
+refdes=R1
+T 44300 46700 5 10 1 1 0 0 1
+value=10k
+}
+C 44000 44000 1 0 0 nc-right-1.sym
+{
+T 44100 44500 5 10 0 0 0 0 1
+value=NoConnection
+T 44100 44700 5 10 0 0 0 0 1
+device=DRC_Directive
+}
+N 44000 47100 43000 47100 4

qa/data/eeschema/io/geda/gschemrc

@@ -0,0 +1,3 @@
+; gschemrc - project-level gschem configuration
+; This file configures local symbol libraries
+(component-library "gschemrc-symbols")

qa/data/eeschema/io/geda/gschemrc-symbols/gschemrc_resistor.sym

@@ -0,0 +1,28 @@
+v 20130925 2
+B 200 0 500 400 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 300 500 5 10 0 0 0 0 1
+device=RESISTOR
+P 900 200 700 200 1 0 0
+{
+T 700 250 5 8 0 1 0 0 1
+pinnumber=2
+T 700 250 5 8 0 0 0 0 1
+pinseq=2
+T 700 250 5 8 0 1 0 0 1
+pinlabel=2
+T 700 250 5 8 0 1 0 0 1
+pintype=pas
+}
+P 0 200 200 200 1 0 0
+{
+T 100 250 5 8 0 1 0 0 1
+pinnumber=1
+T 100 250 5 8 0 0 0 0 1
+pinseq=1
+T 100 250 5 8 0 1 0 0 1
+pinlabel=1
+T 100 250 5 8 0 1 0 0 1
+pintype=pas
+}
+T 200 500 8 10 1 1 0 0 1
+refdes=R?

qa/data/eeschema/io/geda/gschemrc_test.sch

@@ -0,0 +1,12 @@
+v 20130925 2
+C 40000 40000 1 0 0 gschemrc_resistor.sym
+{
+T 40300 40400 5 10 1 1 0 0 1
+refdes=R1
+T 40300 40900 5 10 0 0 0 0 1
+device=RESISTOR
+T 40300 39700 5 10 1 1 0 0 1
+value=1k
+}
+N 40000 40200 39000 40200 4
+N 40900 40200 41900 40200 4

qa/data/eeschema/io/geda/hierarchy_sub.sch

@@ -0,0 +1,13 @@
+v 20130925 2
+N 40000 45000 42000 45000 4
+{
+T 40000 45500 5 10 1 1 0 0 1
+netname=SUBNET
+}
+C 42000 44600 1 0 0 resistor-1.sym
+{
+T 42400 45200 5 10 1 1 0 0 1
+refdes=R1
+T 42400 45600 5 10 1 1 0 0 1
+value=1k
+}

qa/data/eeschema/io/geda/hierarchy_test.sch

@@ -0,0 +1,9 @@
+v 20130925 2
+C 40000 45000 1 0 0 sub_block.sym
+{
+T 40400 46100 5 10 1 1 0 0 1
+refdes=S1
+T 40400 46500 5 10 1 1 0 0 1
+source=hierarchy_sub.sch
+}
+N 38000 45500 40000 45500 4

qa/data/eeschema/io/geda/legacy_kicad.sch

@@ -0,0 +1 @@
+EESchema Schematic File Version 2

qa/data/eeschema/io/geda/lepton-symbols/lepton_resistor.sym

@@ -0,0 +1,28 @@
+v 20201004 2
+B 200 0 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 300 400 5 10 0 0 0 0 1
+device=RESISTOR
+P 900 100 800 100 1 0 0
+{
+T 800 150 5 8 0 1 0 0 1
+pinnumber=2
+T 800 150 5 8 0 0 0 0 1
+pinseq=2
+T 800 150 5 8 0 1 0 0 1
+pinlabel=2
+T 800 150 5 8 0 1 0 0 1
+pintype=pas
+}
+P 0 100 200 100 1 0 0
+{
+T 100 150 5 8 0 1 0 0 1
+pinnumber=1
+T 100 150 5 8 0 0 0 0 1
+pinseq=1
+T 100 150 5 8 0 1 0 0 1
+pinlabel=1
+T 100 150 5 8 0 1 0 0 1
+pintype=pas
+}
+T 200 300 8 10 1 1 0 0 1
+refdes=R?

qa/data/eeschema/io/geda/lepton.conf

@@ -0,0 +1,5 @@
+# Lepton-EDA configuration file
+; This is a test config for the gEDA importer QA tests
+
+[libs]
+component-library=lepton-symbols

qa/data/eeschema/io/geda/lepton_conf_test.sch

@@ -0,0 +1,9 @@
+v 20201004 2
+C 1000 1000 1 0 0 lepton_resistor.sym
+{
+T 1200 1200 5 10 1 1 0 0 1
+refdes=R1
+T 1200 1000 5 10 1 1 0 0 1
+value=4.7k
+}
+N 900 1100 1000 1100 4

qa/data/eeschema/io/geda/minimal_test.sch

@@ -0,0 +1,42 @@
+v 20130925 2
+C 40000 40000 0 0 0 title-B.sym
+C 44000 47000 1 0 0 resistor-1.sym
+{
+T 44300 47400 5 10 1 1 0 0 1
+refdes=R1
+T 44300 47900 5 10 0 0 0 0 1
+device=RESISTOR
+T 44300 46700 5 10 1 1 0 0 1
+value=10k
+T 44300 47100 5 10 1 1 0 0 1
+footprint=0805
+}
+C 46500 45500 1 90 0 capacitor-1.sym
+{
+T 45800 45700 5 10 1 1 90 0 1
+refdes=C1
+T 46200 45700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 45500 45700 5 10 1 1 90 0 1
+value=100nF
+T 46000 46000 5 10 1 1 0 0 1
+footprint=0603
+T 45800 45700 5 10 0 0 90 0 1
+symversion=0.1
+}
+N 44000 47000 43000 47000 4
+{
+T 43000 47100 5 10 1 1 0 0 1
+netname=INPUT
+}
+N 45900 47000 46500 47000 4
+N 46500 47000 46500 46400 4
+{
+T 46600 46800 5 10 1 1 0 0 1
+netname=MID
+}
+N 46500 45500 46500 44500 4
+{
+T 46600 44800 5 10 1 1 0 0 1
+netname=GND
+}

qa/data/eeschema/io/geda/multipage_page1.sch

@@ -0,0 +1,6 @@
+v 20130925 2
+N 40000 45000 42000 45000 4
+{
+T 40000 45500 5 10 1 1 0 0 1
+netname=NET_A
+}

qa/data/eeschema/io/geda/multipage_page2.sch

@@ -0,0 +1,14 @@
+v 20130925 2
+N 40000 45000 42000 45000 4
+{
+T 40000 45500 5 10 1 1 0 0 1
+netname=NET_B
+}
+N 42000 45000 42000 43000 4
+C 43000 44000 1 0 0 resistor-1.sym
+{
+T 43400 44800 5 10 1 1 0 0 1
+refdes=R2
+T 43400 44300 5 10 1 1 0 0 1
+value=22k
+}

qa/data/eeschema/io/geda/multislot_test.sch

@@ -0,0 +1,39 @@
+v 20130925 2
+C 40000 48000 1 0 0 7400-1.sym
+{
+T 40300 48400 5 10 1 1 0 0 1
+refdes=U1
+T 40300 48200 5 10 0 1 0 0 1
+slot=1
+T 40300 48000 5 10 0 1 0 0 1
+numslots=4
+T 40300 47800 5 10 0 1 0 0 1
+slotdef=1:1,2,3
+T 40300 47600 5 10 0 1 0 0 1
+slotdef=2:4,5,6
+T 40300 47400 5 10 0 1 0 0 1
+slotdef=3:9,10,8
+T 40300 47200 5 10 0 1 0 0 1
+slotdef=4:12,13,11
+T 40300 47000 5 10 1 1 0 0 1
+value=7400
+}
+C 44000 48000 1 0 0 7400-1.sym
+{
+T 44300 48400 5 10 1 1 0 0 1
+refdes=U1
+T 44300 48200 5 10 0 1 0 0 1
+slot=2
+T 44300 48000 5 10 0 1 0 0 1
+numslots=4
+T 44300 47800 5 10 0 1 0 0 1
+slotdef=1:1,2,3
+T 44300 47600 5 10 0 1 0 0 1
+slotdef=2:4,5,6
+T 44300 47400 5 10 0 1 0 0 1
+slotdef=3:9,10,8
+T 44300 47200 5 10 0 1 0 0 1
+slotdef=4:12,13,11
+T 44300 47000 5 10 1 1 0 0 1
+value=7400
+}

qa/data/eeschema/io/geda/old_bus_pin_test.sch

@@ -0,0 +1,4 @@
+v 20020101 1
+U 40000 45000 50000 45000 10
+P 44000 47000 45000 47000 3
+N 40000 45000 38000 45000 4

qa/data/eeschema/io/geda/old_format_test.sch

@@ -0,0 +1,6 @@
+v 20000101 1
+L 1000 1000 3000 1000 3
+B 1000 2000 2000 1000 3
+V 2000 4000 500 3
+A 4000 4000 500 0 180 3
+N 1000 1000 1000 3000 4

qa/data/eeschema/io/geda/old_text_test.sch

@@ -0,0 +1,4 @@
+v 20000301 0
+T 44000 47000 5 10 1 0 0 0
+Hello World
+N 44000 47100 43000 47100 4

qa/data/eeschema/io/geda/overbar_test.sch

@@ -0,0 +1,13 @@
+v 20130925 2
+T 1000 1000 9 10 1 0 0 0 1
+\_ACTIVE\_
+T 1000 1500 9 10 1 0 0 0 1
+DATA\_LOW\_
+T 1000 2000 9 10 1 0 0 0 1
+ACTIVE \_HIGH\_
+T 1000 2500 9 10 1 0 0 0 1
+\\backslash
+T 1000 3000 9 10 1 0 0 0 1
+No overbar here
+T 1000 3500 9 10 1 0 0 0 1
+\_CS\_ and \_WR\_

qa/data/eeschema/io/geda/picture_test.sch

@@ -0,0 +1,5 @@
+v 20130925 2
+G 1000 1000 500 500 0 0 1
+test_image.png
+iVBORw0KGgoAAAANSUhEUgAAAAIAAAACCAIAAAD91JpzAAAAEElEQVR4nGP4z8AARAwQCgAf7gP9i18U1AAAAABJRU5ErkJggg==
+.

qa/data/eeschema/io/geda/power_override_test/gafrc

@@ -0,0 +1,2 @@
+;                                                         -*-Scheme-*-
+(component-library "sym")

qa/data/eeschema/io/geda/power_override_test/power_override_test.sch

@@ -0,0 +1,7 @@
+v 20130925 2
+C 44000 47000 1 0 0 gnd-1.sym
+{
+T 44200 46700 5 10 0 0 0 0 1
+refdes=GND1
+}
+N 44200 47600 44200 48000 4

qa/data/eeschema/io/geda/power_override_test/sym/gnd-1.sym

@@ -0,0 +1,17 @@
+v 20130925 2
+T 0 300 8 10 0 0 0 0 1
+device=GND
+P 200 600 200 300 1 0 0
+{
+T 250 350 5 8 0 1 0 0 1
+pinnumber=1
+T 250 350 5 8 0 0 0 0 1
+pinseq=1
+T 250 350 5 8 0 1 0 0 1
+pinlabel=GND
+T 250 350 5 8 0 1 0 0 1
+pintype=pwr
+}
+L 50 300 350 300 3 0 0 0 -1 -1
+L 100 200 300 200 3 0 0 0 -1 -1
+L 150 100 250 100 3 0 0 0 -1 -1

qa/data/eeschema/io/geda/powermeter.sch

@@ -0,0 +1,592 @@
+v 20130925 2
+C 40000 40000 0 0 0 title-B.sym
+C 49800 44900 1 0 0 CS5463.sym
+{
+T 50495 48595 5 10 1 1 0 0 1
+footprint=SSOP24
+T 50800 48200 5 10 1 1 0 0 1
+device=CS5463
+T 49800 44900 5 10 1 1 0 0 1
+refdes=U1
+T 50300 48800 5 10 1 0 0 0 1
+symversion=0.1
+}
+N 50500 45100 52100 45100 4
+{
+T 50500 45100 5 10 1 1 0 0 1
+netname=GND
+}
+C 49300 45100 1 90 0 capacitor-1.sym
+{
+T 48600 45300 5 10 0 0 90 0 1
+device=CAPACITOR
+T 48800 45300 5 10 1 1 90 0 1
+refdes=C1
+T 48400 45300 5 10 0 0 90 0 1
+symversion=0.1
+T 48900 45600 5 10 1 1 0 0 1
+footprint=1812
+T 48900 45300 5 10 1 1 0 0 1
+value=22nF
+}
+C 47300 44500 1 90 0 capacitor-1.sym
+{
+T 46600 44700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 46800 44700 5 10 1 1 90 0 1
+refdes=C3
+T 46400 44700 5 10 0 0 90 0 1
+symversion=0.1
+T 47100 44500 5 10 1 1 90 0 1
+footprint=0603
+T 47300 44500 5 10 1 1 90 0 1
+value=220pF
+}
+N 49800 45800 49700 45800 4
+N 49700 45100 49700 45800 4
+N 49100 45100 49700 45100 4
+C 49800 44000 1 90 0 capacitor-1.sym
+{
+T 49100 44200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 49300 44200 5 10 1 1 90 0 1
+refdes=C2
+T 48900 44200 5 10 0 0 90 0 1
+symversion=0.1
+T 49400 44500 5 10 1 1 0 0 1
+footprint=0603
+T 49400 44200 5 10 1 1 0 0 1
+value=220p
+}
+N 49600 44900 49600 45100 4
+N 50500 44000 50500 45100 4
+C 48700 47800 1 0 0 xtal.sym
+{
+T 48795 47850 5 10 0 1 0 0 1
+device=XTAL
+T 48695 48549 5 10 1 1 0 0 1
+footprint=HC49SMD
+T 48895 47850 5 10 1 1 0 0 1
+refdes=X1
+}
+N 49800 47900 49500 47900 4
+N 49500 47900 49500 48200 4
+N 49800 47700 48700 47700 4
+N 48700 47700 48700 48200 4
+C 49500 49300 1 0 0 capacitor-1.sym
+{
+T 49700 50000 5 10 0 0 0 0 1
+device=CAPACITOR
+T 49700 49800 5 10 1 1 0 0 1
+refdes=C4
+T 49700 50200 5 10 0 0 0 0 1
+symversion=0.1
+T 49500 49300 5 10 1 1 0 0 1
+footprint=0603
+T 49500 49600 5 10 1 1 0 0 1
+value=100nf
+}
+N 50500 48600 50500 49500 4
+{
+T 50400 49200 5 10 1 1 0 0 1
+netname=5v
+}
+N 50500 49500 50400 49500 4
+N 49500 49500 48900 49500 4
+{
+T 49000 49500 5 10 1 1 0 0 1
+netname=GND
+}
+C 51700 49300 1 0 0 capacitor-1.sym
+{
+T 51900 50000 5 10 0 0 0 0 1
+device=CAPACITOR
+T 51900 49800 5 10 1 1 0 0 1
+refdes=C5
+T 51900 50200 5 10 0 0 0 0 1
+symversion=0.1
+T 51700 49300 5 10 1 1 0 0 1
+footprint=0603
+T 51600 49600 5 10 1 1 0 0 1
+value=100nF
+}
+N 51600 48600 51600 49500 4
+{
+T 51600 48600 5 10 1 0 0 0 1
+netname=3v
+}
+N 51600 49500 51700 49500 4
+N 52600 49500 53100 49500 4
+{
+T 52600 49500 5 10 1 1 0 0 1
+netname=GND
+}
+N 41200 50600 42300 50600 4
+{
+T 41200 50600 5 10 1 1 0 0 1
+netname=5v
+}
+N 52300 45800 52300 46000 4
+C 52100 44900 1 0 0 capacitor-1.sym
+{
+T 52300 45600 5 10 0 0 0 0 1
+device=CAPACITOR
+T 52300 45400 5 10 1 1 0 0 1
+refdes=C6
+T 52300 45800 5 10 0 0 0 0 1
+symversion=0.1
+T 52100 45100 5 10 1 1 0 0 1
+footprint=0603
+T 52100 44900 5 10 1 1 0 0 1
+value=100nF
+}
+N 53000 45100 53000 45800 4
+N 53000 45800 52300 45800 4
+C 52700 46800 1 0 0 resistor-1.sym
+{
+T 53000 47200 5 10 0 0 0 0 1
+device=RESISTOR
+T 53000 46900 5 10 1 1 0 0 1
+refdes=R1
+T 52900 46700 5 10 1 1 0 0 1
+footprint=0805
+T 52700 46800 5 10 1 1 0 0 1
+value=150
+}
+C 52700 47100 1 0 0 resistor-1.sym
+{
+T 53000 47500 5 10 0 0 0 0 1
+device=RESISTOR
+T 52900 47400 5 10 1 1 0 0 1
+refdes=R2
+T 53100 47300 5 10 1 1 0 0 1
+footprint=0805
+T 52700 47300 5 10 1 1 0 0 1
+value=1k
+}
+N 52700 46900 52300 46900 4
+N 52300 47100 52700 47100 4
+N 52700 47100 52700 47200 4
+N 53600 46900 53600 47200 4
+{
+T 53600 46900 5 10 1 1 0 0 1
+netname=5v
+}
+C 43500 49400 1 0 0 DS1117-3_3.sym
+{
+T 43500 49395 5 10 0 1 0 0 1
+footprint=SOT223
+T 43500 49395 5 10 0 1 0 0 1
+device=DS117-3.3
+T 43200 50200 5 10 1 1 0 0 1
+refdes=U2
+}
+N 41200 49600 42300 49600 4
+{
+T 41200 49600 5 10 1 1 0 0 1
+netname=GND
+}
+N 43700 49400 43700 48600 4
+{
+T 43600 48800 5 10 1 1 90 0 1
+netname=GND
+}
+N 44000 49400 44000 48600 4
+{
+T 44000 48900 5 10 1 1 90 0 1
+netname=3v
+}
+N 44300 49400 44300 48600 4
+{
+T 44300 48900 5 10 1 1 90 0 1
+netname=5v
+}
+N 49800 47500 48900 47500 4
+{
+T 49100 47500 5 10 1 1 0 0 1
+netname=SCLK
+}
+N 49800 47300 48900 47300 4
+{
+T 49100 47300 5 10 1 1 0 0 1
+netname=SDO
+}
+N 49800 47100 48900 47100 4
+{
+T 49100 47100 5 10 1 1 0 0 1
+netname=SDI
+}
+N 49800 46900 48900 46900 4
+{
+T 49100 46900 5 10 1 1 0 0 1
+netname=CS
+}
+N 41200 46600 42200 46600 4
+{
+T 41200 46600 5 10 1 1 0 0 1
+netname=SCLK
+}
+N 41200 45600 42200 45600 4
+{
+T 41200 45600 5 10 1 1 0 0 1
+netname=SDI
+}
+N 41200 44500 42200 44500 4
+{
+T 41200 44500 5 10 1 1 0 0 1
+netname=SDO
+}
+N 41200 43400 42200 43400 4
+{
+T 41200 43400 5 10 1 1 0 0 1
+netname=CS
+}
+N 41200 48500 42400 48500 4
+{
+T 41200 48500 5 10 1 1 0 0 1
+netname=3v
+}
+T 41200 41600 8 10 1 1 0 0 1
+value=LINE_IN
+N 41200 41800 42100 41800 4
+{
+T 41200 41800 5 10 1 1 0 0 1
+netname=P1_A
+}
+C 42100 41700 1 0 0 resistor-1.sym
+{
+T 42400 42100 5 10 0 0 0 0 1
+device=RESISTOR
+T 42300 42000 5 10 1 1 0 0 1
+refdes=R3
+T 42100 41700 5 10 1 1 0 0 1
+footprint=1206
+T 42500 41900 5 10 1 1 0 0 1
+value=0.5
+}
+N 43000 41800 43800 41800 4
+{
+T 43000 41800 5 10 1 1 0 0 1
+netname=P1_B
+}
+C 44800 42600 1 90 1 BT136.sym
+{
+T 44105 41405 5 10 0 1 270 2 1
+footprint=TO252
+T 44405 41405 5 10 0 1 270 2 1
+device=TRIAC
+T 44800 42600 5 10 1 1 0 0 1
+refdes=T1
+}
+N 41200 40700 45900 40700 4
+{
+T 41200 40700 5 10 1 1 0 0 1
+netname=P2
+}
+N 44800 41800 45900 41800 4
+C 44800 46500 1 90 1 MOC3021.sym
+{
+T 44800 46505 5 10 0 1 270 2 1
+footprint=730C-04
+T 44827 46505 5 10 0 1 270 2 1
+device=MOC3023
+T 44800 46500 5 10 1 1 0 0 1
+refdes=U3
+}
+N 44600 42600 44600 43500 4
+C 43600 42500 1 90 0 resistor-1.sym
+{
+T 43200 42800 5 10 0 0 90 0 1
+device=RESISTOR
+T 43300 42700 5 10 1 1 90 0 1
+refdes=R4
+T 43800 42900 5 10 1 1 90 0 1
+footprint=1206
+T 43400 43000 5 10 1 1 90 0 1
+value=360
+}
+N 43500 43400 43500 43500 4
+N 43500 42500 43500 41800 4
+C 42500 47400 1 0 0 resistor-1.sym
+{
+T 42800 47800 5 10 0 0 0 0 1
+device=RESISTOR
+T 42700 47700 5 10 1 1 0 0 1
+refdes=R5
+T 42900 47400 5 10 1 1 0 0 1
+footprint=0805
+T 42400 47600 5 10 1 1 0 0 1
+value=100
+}
+N 41200 47500 42500 47500 4
+N 43400 47500 43500 47500 4
+N 43500 47500 43500 46500 4
+N 44600 46500 44600 47500 4
+{
+T 44600 46600 5 10 1 1 90 0 1
+netname=GND
+}
+C 48200 45000 1 0 0 resistor-1.sym
+{
+T 48500 45400 5 10 0 0 0 0 1
+device=RESISTOR
+T 48100 44900 5 10 1 1 0 0 1
+refdes=R10
+T 48600 44800 5 10 1 1 0 0 1
+footprint=0805
+T 48200 45200 5 10 1 1 0 0 1
+value=1k
+}
+N 48200 45100 47700 45100 4
+{
+T 47700 45100 5 10 1 1 0 0 1
+netname=P1_A
+}
+N 46800 46000 49800 46000 4
+N 47100 46000 47100 45400 4
+N 47100 44500 47100 44000 4
+N 47100 44000 50500 44000 4
+C 45900 45900 1 0 0 resistor-1.sym
+{
+T 46200 46300 5 10 0 0 0 0 1
+device=RESISTOR
+T 46100 46200 5 10 1 1 0 0 1
+refdes=R6
+T 46200 45900 5 10 1 1 0 0 1
+footprint=0805
+T 45900 46100 5 10 1 1 0 0 1
+value=1k
+}
+N 45900 46000 45200 46000 4
+{
+T 45400 46000 5 10 1 1 0 0 1
+netname=P1_B
+}
+C 48100 46300 1 90 0 capacitor-1.sym
+{
+T 47400 46500 5 10 0 0 90 0 1
+device=CAPACITOR
+T 47600 46500 5 10 1 1 90 0 1
+refdes=C7
+T 47200 46500 5 10 0 0 90 0 1
+symversion=0.1
+T 47700 46800 5 10 1 1 0 0 1
+footprint=0603
+T 47700 46500 5 10 1 1 0 0 1
+value=220p
+}
+C 48100 47500 1 90 0 capacitor-1.sym
+{
+T 47400 47700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 47600 47700 5 10 1 1 90 0 1
+refdes=C8
+T 47200 47700 5 10 0 0 90 0 1
+symversion=0.1
+T 47700 48000 5 10 1 1 0 0 1
+footprint=0603
+T 47700 47700 5 10 1 1 0 0 1
+value=220p
+}
+N 47200 46300 49800 46300 4
+N 49800 46500 48300 46500 4
+N 48300 46500 48300 48400 4
+N 46200 48400 48300 48400 4
+N 47900 47200 47900 47500 4
+{
+T 47900 47100 5 10 1 1 90 0 1
+netname=GND
+}
+C 47400 47000 1 90 0 capacitor-1.sym
+{
+T 46700 47200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 46900 47200 5 10 1 1 90 0 1
+refdes=C9
+T 46500 47200 5 10 0 0 90 0 1
+symversion=0.1
+T 47000 47500 5 10 1 1 0 0 1
+footprint=1812
+T 47000 47200 5 10 1 1 0 0 1
+value=22nF
+}
+N 47200 47900 47200 48400 4
+N 47200 47000 47200 46300 4
+C 46100 46600 1 0 0 resistor-1.sym
+{
+T 46400 47000 5 10 0 0 0 0 1
+device=RESISTOR
+T 46300 46900 5 10 1 1 0 0 1
+refdes=R7
+T 46400 46600 5 10 1 1 0 0 1
+footprint=0805
+T 46100 46800 5 10 1 1 0 0 1
+value=1k
+}
+N 47000 46700 47200 46700 4
+N 46100 46700 45500 46700 4
+N 45500 46000 45500 46900 4
+C 45600 46900 1 90 0 resistor-1.sym
+{
+T 45200 47200 5 10 0 0 90 0 1
+device=RESISTOR
+T 45300 47400 5 10 1 1 90 0 1
+refdes=R8
+T 45600 47200 5 10 1 1 90 0 1
+footprint=0805
+T 45400 46900 5 10 1 1 90 0 1
+value=100
+}
+C 45600 48300 1 90 0 resistor-1.sym
+{
+T 45200 48600 5 10 0 0 90 0 1
+device=RESISTOR
+T 45300 48800 5 10 1 1 90 0 1
+refdes=R9
+T 45600 48600 5 10 1 1 90 0 1
+footprint=0805
+T 45400 48100 5 10 1 1 90 0 1
+value=200k
+}
+N 45500 48300 45500 47800 4
+N 46200 48400 46200 48000 4
+N 46200 48000 45500 48000 4
+N 45500 49200 45500 49700 4
+{
+T 45500 49200 5 10 1 1 0 0 1
+netname=P2
+}
+N 49200 44900 49100 45100 4
+N 49200 44900 49100 45100 4
+C 40300 50500 1 0 0 terminal-1.sym
+{
+T 40610 51250 5 10 0 0 0 0 1
+device=terminal
+T 40850 50750 5 10 1 1 0 6 1
+refdes=T13
+T 40500 50300 5 10 1 1 0 0 1
+footprint=PAD40
+T 40400 50500 5 10 1 1 0 0 1
+value=5V
+}
+C 40300 49500 1 0 0 terminal-1.sym
+{
+T 40610 50250 5 10 0 0 0 0 1
+device=terminal
+T 40750 49750 5 10 1 1 0 6 1
+refdes=T2
+T 40600 49300 5 10 1 1 0 0 1
+footprint=PAD40
+T 40200 49500 5 10 1 1 0 0 1
+value=GND
+}
+C 40300 48400 1 0 0 terminal-1.sym
+{
+T 40610 49150 5 10 0 0 0 0 1
+device=terminal
+T 40750 48650 5 10 1 1 0 6 1
+refdes=T3
+T 40600 48200 5 10 1 1 0 0 1
+footprint=PAD40
+T 40200 48400 5 10 1 1 0 0 1
+value=3v
+}
+C 40300 47400 1 0 0 terminal-1.sym
+{
+T 40610 48150 5 10 0 0 0 0 1
+device=terminal
+T 40750 47650 5 10 1 1 0 6 1
+refdes=T4
+T 40600 47200 5 10 1 1 0 0 1
+footprint=PAD20
+T 40200 47400 5 10 1 1 0 0 1
+value=ON
+}
+C 40300 46500 1 0 0 terminal-1.sym
+{
+T 40610 47250 5 10 0 0 0 0 1
+device=terminal
+T 40750 46750 5 10 1 1 0 6 1
+refdes=T5
+T 40600 46300 5 10 1 1 0 0 1
+footprint=PAD20
+T 40200 46500 5 10 1 1 0 0 1
+value=SCLK
+}
+C 40300 45500 1 0 0 terminal-1.sym
+{
+T 40610 46250 5 10 0 0 0 0 1
+device=terminal
+T 40750 45750 5 10 1 1 0 6 1
+refdes=T6
+T 40600 45300 5 10 1 1 0 0 1
+footprint=PAD20
+T 40200 45500 5 10 1 1 0 0 1
+value=SDI
+}
+C 40300 44400 1 0 0 terminal-1.sym
+{
+T 40610 45150 5 10 0 0 0 0 1
+device=terminal
+T 40750 44650 5 10 1 1 0 6 1
+refdes=T7
+T 40600 44200 5 10 1 1 0 0 1
+footprint=PAD20
+T 40200 44400 5 10 1 1 0 0 1
+value=SDO
+}
+C 40300 43300 1 0 0 terminal-1.sym
+{
+T 40610 44050 5 10 0 0 0 0 1
+device=terminal
+T 40750 43550 5 10 1 1 0 6 1
+refdes=T8
+T 40600 43100 5 10 1 1 0 0 1
+footprint=PAD20
+T 40200 43300 5 10 1 1 0 0 1
+value=CS
+}
+C 40300 41700 1 0 0 terminal-1.sym
+{
+T 40610 42450 5 10 0 0 0 0 1
+device=terminal
+T 40750 41950 5 10 1 1 0 6 1
+refdes=T9
+T 40600 41500 5 10 1 1 0 0 1
+footprint=PAD60
+T 39900 41700 5 10 1 1 0 0 1
+value=LINE_IN
+}
+C 40300 40600 1 0 0 terminal-1.sym
+{
+T 40610 41350 5 10 0 0 0 0 1
+device=terminal
+T 40750 40850 5 10 1 1 0 6 1
+refdes=T10
+T 40600 40400 5 10 1 1 0 0 1
+footprint=PAD60
+T 39900 40600 5 10 1 1 0 0 1
+value=NEUTRE
+}
+C 46800 40800 1 180 0 terminal-1.sym
+{
+T 46490 40050 5 10 0 0 180 0 1
+device=terminal
+T 46350 40550 5 10 1 1 180 6 1
+refdes=T12
+T 46500 41000 5 10 1 1 180 0 1
+footprint=PAD60
+T 46900 40800 5 10 1 1 180 0 1
+value=NEUTRE
+}
+C 46800 41900 1 180 0 terminal-1.sym
+{
+T 46490 41150 5 10 0 0 180 0 1
+device=terminal
+T 46350 41650 5 10 1 1 180 6 1
+refdes=T11
+T 46500 42100 5 10 1 1 180 0 1
+footprint=PAD60
+T 46900 41900 5 10 1 1 180 0 1
+value=LINE_OUT
+}

qa/data/eeschema/io/geda/priority_test/gafrc

@@ -0,0 +1 @@
+(component-library "sym")

qa/data/eeschema/io/geda/priority_test/priority_test.sch

@@ -0,0 +1,8 @@
+v 20130925 2
+C 40000 40000 1 0 0 resistor-1.sym
+{
+T 40300 40400 5 10 1 1 0 0 1
+refdes=R1
+T 40300 40600 5 10 1 1 0 0 1
+value=1k
+}

qa/data/eeschema/io/geda/priority_test/sym/resistor-1.sym

@@ -0,0 +1,39 @@
+v 20130925 2
+T 300 400 8 10 1 1 0 0 1
+refdes=R?
+T 300 -100 8 10 0 0 0 0 1
+device=RESISTOR
+P 0 200 200 200 1 0 0
+{
+T 100 250 5 8 0 1 0 0 1
+pinnumber=1
+T 100 250 5 8 0 0 0 0 1
+pinseq=1
+T 100 250 5 8 0 1 0 0 1
+pinlabel=1
+T 100 250 5 8 0 1 0 0 1
+pintype=pas
+}
+P 900 200 700 200 1 0 0
+{
+T 800 250 5 8 0 1 0 0 1
+pinnumber=2
+T 800 250 5 8 0 0 0 0 1
+pinseq=2
+T 800 250 5 8 0 1 0 0 1
+pinlabel=2
+T 800 250 5 8 0 1 0 0 1
+pintype=pas
+}
+P 450 0 450 100 1 0 0
+{
+T 500 50 5 8 0 1 0 0 1
+pinnumber=3
+T 500 50 5 8 0 0 0 0 1
+pinseq=3
+T 500 50 5 8 0 1 0 0 1
+pinlabel=3
+T 500 50 5 8 0 1 0 0 1
+pintype=pas
+}
+B 200 100 500 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1

qa/data/eeschema/io/geda/props_test.sch

@@ -0,0 +1,12 @@
+v 20130925 2
+C 40000 40000 1 0 0 props_resistor.sym
+{
+T 40300 40400 5 10 1 1 0 0 1
+refdes=R1
+T 40300 40900 5 10 0 0 0 0 1
+device=RESISTOR
+T 40300 39700 5 10 1 1 0 0 1
+value=2.2k
+}
+N 40000 40200 39000 40200 4
+N 40900 40200 41900 40200 4

qa/data/eeschema/io/geda/random.sch

@@ -0,0 +1 @@
+this is not a schematic

qa/data/eeschema/io/geda/relative_path_test.sch

@@ -0,0 +1,7 @@
+v 20130925 2
+H 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 2
+M 1000 1000
+l 500 0
+H 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1 2
+M 2000 2000
+L 2500 2000

qa/data/eeschema/io/geda/symver_resistor.sym

@@ -0,0 +1,30 @@
+v 20201004 2
+B 200 0 600 200 3 0 0 0 -1 -1 0 -1 -1 -1 -1 -1
+T 300 400 5 10 0 0 0 0 1
+device=RESISTOR
+T 300 600 5 10 0 0 0 0 1
+symversion=2.0
+P 900 100 800 100 1 0 0
+{
+T 800 150 5 8 0 1 0 0 1
+pinnumber=2
+T 800 150 5 8 0 0 0 0 1
+pinseq=2
+T 800 150 5 8 0 1 0 0 1
+pinlabel=2
+T 800 150 5 8 0 1 0 0 1
+pintype=pas
+}
+P 0 100 200 100 1 0 0
+{
+T 100 150 5 8 0 1 0 0 1
+pinnumber=1
+T 100 150 5 8 0 0 0 0 1
+pinseq=1
+T 100 150 5 8 0 1 0 0 1
+pinlabel=1
+T 100 150 5 8 0 1 0 0 1
+pintype=pas
+}
+T 200 300 8 10 1 1 0 0 1
+refdes=R?

qa/data/eeschema/io/geda/symversion_test.sch

@@ -0,0 +1,11 @@
+v 20201004 2
+C 1000 1000 1 0 0 symver_resistor.sym
+{
+T 1200 1200 5 10 1 1 0 0 1
+refdes=R1
+T 1200 1000 5 10 1 1 0 0 1
+value=10k
+T 1200 800 5 10 0 0 0 0 1
+symversion=1.0
+}
+N 900 1100 1000 1100 4

qa/data/eeschema/io/geda/text_angle_test.sch

@@ -0,0 +1,11 @@
+v 20130925 2
+T 1000 1000 9 10 1 0 45 0 1
+Angled45
+T 2000 2000 9 10 1 0 135 0 1
+Angled135
+T 3000 3000 9 10 1 0 200 0 1
+Angled200
+T 4000 4000 9 10 1 0 315 0 1
+Angled315
+T 5000 5000 9 10 1 0 90 0 1
+Exact90

qa/data/eeschema/io/geda/text_size_test.sch

@@ -0,0 +1,5 @@
+v 20130925 2
+T 1000 1000 9 10 1 0 0 0 1
+Hello World
+T 2000 2000 9 20 1 0 0 0 1
+Big Text

qa/data/eeschema/io/geda/tjunction_test.sch

@@ -0,0 +1,5 @@
+v 20130925 2
+N 44000 47000 48000 47000 4
+N 46000 47000 46000 45000 4
+N 44000 45000 48000 45000 4
+N 46000 45000 46000 43000 4

qa/data/eeschema/io/geda/very_old_text_test.sch

@@ -0,0 +1,4 @@
+v 19991231 0
+T 44000 47000 5 10 1 0 0
+Old Text
+N 44000 47100 43000 47100 4

qa/data/eeschema/io/geda/zpowerMeter.sch

@@ -0,0 +1,728 @@
+v 20130925 2
+C 40000 40000 0 0 0 title-B.sym
+C 40000 44300 1 0 0 terminal-1.sym
+{
+T 40310 45050 5 10 0 0 0 0 1
+device=terminal
+T 40310 44900 5 10 0 0 0 0 1
+footprint=CONNECTOR 1 1
+T 40250 44350 5 10 1 1 0 6 1
+refdes=T?
+}
+C 40000 43300 1 0 0 terminal-1.sym
+{
+T 40310 44050 5 10 0 0 0 0 1
+device=terminal
+T 40310 43900 5 10 0 0 0 0 1
+footprint=CONNECTOR 1 1
+T 40250 43350 5 10 1 1 0 6 1
+refdes=T?
+}
+T 40500 44000 9 12 1 0 0 0 1
+POWER LINE 220V
+B 44800 40700 1500 600 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
+T 44900 40900 9 12 1 0 0 0 1
+LED DRIVER
+P 44400 41200 44800 41200 1 0 0
+{
+T 44500 41250 5 10 0 0 0 0 1
+pintype=unknown
+T 44455 41295 9 10 1 1 0 0 1
+pinlabel=POWER
+T 44705 41245 5 10 0 1 0 6 1
+pinnumber=0
+T 44500 41250 5 10 0 0 0 0 1
+pinseq=0
+}
+P 44400 40800 44800 40800 1 0 0
+{
+T 44500 40850 5 10 0 0 0 0 1
+pintype=unknown
+T 44455 40595 9 10 1 1 0 0 1
+pinlabel=POWER
+T 44705 40845 5 10 0 1 0 6 1
+pinnumber=0
+T 44500 40850 5 10 0 0 0 0 1
+pinseq=0
+}
+N 40900 43400 42700 43400 4
+{
+T 41700 43455 5 10 1 1 0 3 1
+netname=P2
+}
+N 42300 40800 44400 40800 4
+C 47100 41200 1 0 0 led-1.sym
+{
+T 47900 41800 5 10 0 0 0 0 1
+device=LED
+T 47300 41600 5 10 1 1 0 0 1
+refdes=LED?
+T 47900 42000 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 48700 41200 1 0 0 led-1.sym
+{
+T 49500 41800 5 10 0 0 0 0 1
+device=LED
+T 49000 41600 5 10 1 1 0 0 1
+refdes=LED?
+T 49500 42000 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 50200 41200 1 0 0 led-1.sym
+{
+T 51000 41800 5 10 0 0 0 0 1
+device=LED
+T 50500 41600 5 10 1 1 0 0 1
+refdes=LED?
+T 51000 42000 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 51600 41200 1 0 0 led-1.sym
+{
+T 52400 41800 5 10 0 0 0 0 1
+device=LED
+T 51800 41600 5 10 1 1 0 0 1
+refdes=LED?
+T 52400 42000 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 52800 41200 1 0 0 led-1.sym
+{
+T 53600 41800 5 10 0 0 0 0 1
+device=LED
+T 53000 41600 5 10 1 1 0 0 1
+refdes=LED?
+T 53600 42000 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 48000 40300 1 0 1 led-1.sym
+{
+T 47200 40900 5 10 0 0 0 6 1
+device=LED
+T 47200 41100 5 10 0 0 0 6 1
+symversion=0.1
+T 47800 40800 5 10 1 1 0 6 1
+refdes=LED?
+}
+C 49600 40300 1 0 1 led-1.sym
+{
+T 48800 40900 5 10 0 0 0 6 1
+device=LED
+T 48800 41100 5 10 0 0 0 6 1
+symversion=0.1
+T 49400 40700 5 10 1 1 0 6 1
+refdes=LED?
+}
+C 51300 40300 1 0 1 led-1.sym
+{
+T 50500 40900 5 10 0 0 0 6 1
+device=LED
+T 50500 41100 5 10 0 0 0 6 1
+symversion=0.1
+T 51100 40700 5 10 1 1 0 6 1
+refdes=LED?
+}
+C 52500 40300 1 0 1 led-1.sym
+{
+T 51700 40900 5 10 0 0 0 6 1
+device=LED
+T 51700 41100 5 10 0 0 0 6 1
+symversion=0.1
+T 52300 40700 5 10 1 1 0 6 1
+refdes=LED?
+}
+C 53700 40300 1 0 1 led-1.sym
+{
+T 52900 40900 5 10 0 0 0 6 1
+device=LED
+T 52900 41100 5 10 0 0 0 6 1
+symversion=0.1
+T 53500 40700 5 10 1 1 0 6 1
+refdes=LED?
+}
+N 48000 41400 48700 41400 4
+N 49600 41400 50200 41400 4
+N 51100 41400 51600 41400 4
+N 52500 41400 52800 41400 4
+N 53700 41400 54300 41400 4
+N 54300 41400 54300 40500 4
+N 54300 40500 53700 40500 4
+N 52800 40500 52500 40500 4
+N 51600 40500 51300 40500 4
+N 50400 40500 49600 40500 4
+N 48700 40500 48000 40500 4
+P 46600 41200 46300 41200 1 0 0
+{
+T 46500 41250 5 10 0 0 0 6 1
+pintype=unknown
+T 46845 41295 9 10 1 1 0 6 1
+pinlabel=PLUS
+T 46395 41245 5 10 0 1 0 0 1
+pinnumber=0
+T 46500 41250 5 10 0 0 0 6 1
+pinseq=0
+}
+P 46600 40800 46300 40800 1 0 0
+{
+T 46500 40850 5 10 0 0 0 6 1
+pintype=unknown
+T 46545 40495 9 10 1 1 0 6 1
+pinlabel=MINUX
+T 46395 40845 5 10 0 1 0 0 1
+pinnumber=0
+T 46500 40850 5 10 0 0 0 6 1
+pinseq=0
+}
+N 46600 40800 47100 40800 4
+N 47100 40800 47100 40500 4
+N 46600 41200 47100 41200 4
+N 47100 41200 47100 41400 4
+T 43400 45000 9 12 1 0 0 0 2
+AC-DC
+5Volt
+B 43200 44900 1000 700 3 0 1 0 -1 -1 0 -1 -1 -1 -1 -1
+P 42800 45500 43200 45500 1 0 0
+{
+T 42900 45550 5 10 0 0 0 0 1
+pintype=unknown
+T 42855 45595 9 10 1 1 0 0 1
+pinlabel=POWER
+T 43105 45545 5 10 0 1 0 6 1
+pinnumber=0
+T 42900 45550 5 10 0 0 0 0 1
+pinseq=0
+}
+P 42800 45000 43200 45000 1 0 0
+{
+T 42900 45050 5 10 0 0 0 0 1
+pintype=unknown
+T 42855 44795 9 10 1 1 0 0 1
+pinlabel=POWER
+T 43105 45045 5 10 0 1 0 6 1
+pinnumber=0
+T 42900 45050 5 10 0 0 0 0 1
+pinseq=0
+}
+P 44500 45500 44200 45500 1 0 0
+{
+T 44400 45550 5 10 0 0 0 6 1
+pintype=unknown
+T 44745 45595 9 10 1 1 0 6 1
+pinlabel=5Volts
+T 44295 45545 5 10 0 1 0 0 1
+pinnumber=0
+T 44400 45550 5 10 0 0 0 6 1
+pinseq=0
+}
+P 44500 45000 44200 45000 1 0 0
+{
+T 44400 45050 5 10 0 0 0 6 1
+pintype=unknown
+T 44745 44795 9 10 1 1 0 6 1
+pinlabel=GND
+T 44295 45045 5 10 0 1 0 0 1
+pinnumber=0
+T 44400 45050 5 10 0 0 0 6 1
+pinseq=0
+}
+C 44400 44400 1 0 0 gnd-1.sym
+N 44500 45000 44500 44700 4
+N 42800 45000 42700 45000 4
+N 42800 45500 42300 45500 4
+N 44600 46400 44600 45500 4
+N 44600 45500 44500 45500 4
+C 43700 46000 1 0 0 generic-power.sym
+{
+T 43900 46250 5 10 1 1 0 3 1
+net=5Volt
+}
+N 43900 46000 43900 45900 4
+N 43900 45900 44600 45900 4
+C 45100 45300 1 0 0 gnd-1.sym
+N 45200 45600 45200 46400 4
+C 45800 45900 1 0 0 generic-power.sym
+{
+T 46000 46150 5 10 1 1 0 3 1
+net=3.3Volt
+}
+N 44900 46400 44900 45900 4
+N 44900 45900 46000 45900 4
+C 44400 46400 1 0 0 DS1117-3_3.sym
+{
+T 44400 46395 5 10 0 1 0 0 1
+footprint=SOT-223
+T 44400 46395 5 10 0 1 0 0 1
+device=none
+}
+C 41400 46900 1 0 0 CC2530Module.sym
+{
+T 40995 49995 5 10 1 1 0 0 1
+device=CC2530-MODULE
+T 41395 46995 5 10 0 1 0 0 1
+footprint=DIP24
+}
+C 42800 46500 1 0 0 gnd-1.sym
+N 42900 46900 42900 46800 4
+C 42600 50500 1 0 0 generic-power.sym
+{
+T 42800 50750 5 10 1 1 0 3 1
+net=3.3Volt
+}
+N 42800 50500 42800 50200 4
+C 46200 48000 1 90 0 resistor-1.sym
+{
+T 45800 48300 5 10 0 0 90 0 1
+device=RESISTOR
+T 45900 48200 5 10 1 1 90 0 1
+refdes=R8
+}
+C 45900 49100 1 0 0 generic-power.sym
+{
+T 46100 49350 5 10 1 1 0 3 1
+net=3.3Volt
+}
+N 46100 47900 46100 48000 4
+N 46100 49100 46100 48900 4
+C 46300 47900 1 0 0 switch-spst-1.sym
+{
+T 46700 48600 5 10 0 0 0 0 1
+device=SPST
+T 46600 48200 5 10 1 1 0 0 1
+refdes=S?
+}
+C 47000 47200 1 0 0 gnd-1.sym
+N 47100 47900 47100 47500 4
+N 44000 47900 46300 47900 4
+C 44000 42500 1 0 1 BT136.sym
+{
+T 42805 43195 5 10 0 1 0 6 1
+footprint=TO92
+T 42805 42895 5 10 0 1 0 6 1
+device=none
+T 44000 42500 5 10 1 1 0 0 1
+footprint=TO-252
+}
+N 43200 43500 43200 44400 4
+N 43200 42500 43200 41200 4
+N 43200 41200 44400 41200 4
+T 42900 43900 9 12 1 0 0 0 1
+BT136
+C 47600 42400 1 0 1 MOC3021.sym
+{
+T 47605 42400 5 10 0 1 0 6 1
+footprint=DIP6
+T 47605 42373 5 10 0 1 0 6 1
+device=none
+T 47600 42400 5 10 1 1 0 0 1
+footprint=SOP6
+}
+C 43500 43600 1 0 0 resistor-1.sym
+{
+T 43800 44000 5 10 0 0 0 0 1
+device=RESISTOR
+T 43700 43900 5 10 1 1 0 0 1
+refdes=R?
+T 43700 43500 5 10 1 1 0 0 1
+value=360
+T 43500 43600 5 10 1 1 0 0 1
+footprint=1206
+}
+N 43500 43700 43200 43700 4
+N 44400 43700 44600 43700 4
+N 44600 42600 44000 42600 4
+N 44000 42600 44000 42700 4
+C 47700 42100 1 0 0 gnd-1.sym
+N 47600 42600 47800 42600 4
+N 47800 42600 47800 42400 4
+C 47900 43600 1 0 0 resistor-1.sym
+{
+T 48200 44000 5 10 0 0 0 0 1
+device=RESISTOR
+T 48100 43900 5 10 1 1 0 0 1
+refdes=R7
+T 48100 43500 5 10 1 1 0 0 1
+value=70
+}
+N 47600 43700 47900 43700 4
+N 48800 43700 49600 43700 4
+{
+T 49200 43755 5 10 1 1 0 3 1
+netname=LIGHT_ON
+}
+N 41400 49600 40300 49600 4
+{
+T 40850 49655 5 10 1 1 0 3 1
+netname=LIGHT_ON
+}
+C 52300 45800 1 0 0 CS5463.sym
+{
+T 52295 45795 5 10 0 1 0 0 1
+footprint=24LSSOP
+}
+C 53500 45300 1 0 0 gnd-1.sym
+N 53600 45600 53600 46000 4
+N 53000 46000 54100 46000 4
+C 53900 50000 1 0 0 generic-power.sym
+{
+T 54100 50250 5 10 1 1 0 3 1
+net=3.3Volt
+}
+C 52800 50000 1 0 0 generic-power.sym
+{
+T 52800 50200 5 10 1 1 0 0 1
+net=5Volt
+}
+N 53000 49500 53000 50000 4
+N 54100 49500 54100 50000 4
+C 55100 47700 1 0 0 resistor-1.sym
+{
+T 55400 48100 5 10 0 0 0 0 1
+device=RESISTOR
+T 55300 48000 5 10 1 1 0 0 1
+refdes=R?
+T 55300 47600 5 10 1 1 0 0 1
+value=150
+}
+N 55100 47800 54800 47800 4
+N 56000 47800 56300 47800 4
+N 56300 47800 56300 49900 4
+N 54100 49900 56300 49900 4
+T 53400 47450 8 10 0 1 0 3 1
+net=Vcc:1
+C 54400 49400 1 0 0 capacitor-1.sym
+{
+T 54600 50100 5 10 0 0 0 0 1
+device=CAPACITOR
+T 54600 49600 5 10 1 1 0 0 1
+refdes=C2
+T 54600 50300 5 10 0 0 0 0 1
+symversion=0.1
+T 54400 49400 5 10 1 1 0 0 1
+value=100n
+}
+N 54400 49600 54100 49600 4
+C 55300 49200 1 0 0 gnd-1.sym
+N 55300 49600 55400 49600 4
+N 55400 49600 55400 49500 4
+C 53800 49400 1 0 0 gnd-1.sym
+N 54800 46700 55000 46700 4
+N 55000 46600 55000 46900 4
+N 55000 46900 54800 46900 4
+C 55200 45700 1 90 0 capacitor-1.sym
+{
+T 54500 45900 5 10 0 0 90 0 1
+device=CAPACITOR
+T 54900 46100 5 10 1 1 180 0 1
+refdes=C3
+T 54300 45900 5 10 0 0 90 0 1
+symversion=0.1
+T 55000 46300 5 10 1 1 180 0 1
+value=100n
+}
+N 55000 45700 53600 45700 4
+N 42700 44900 42700 43400 4
+C 41200 44300 1 0 0 resistor-1.sym
+{
+T 41500 44700 5 10 0 0 0 0 1
+device=RESISTOR
+T 41400 44600 5 10 1 1 0 0 1
+refdes=R1
+T 41400 44200 5 10 1 1 0 0 1
+value=0.04
+T 41200 44300 5 10 1 0 0 0 1
+footprint=2512
+}
+N 42100 44400 42300 44400 4
+{
+T 42200 44455 5 10 1 1 0 3 1
+netname=P1_B
+}
+N 40900 44400 41200 44400 4
+{
+T 41050 44455 5 10 1 1 0 3 1
+netname=P1_A
+}
+C 51800 46000 1 90 0 capacitor-1.sym
+{
+T 51100 46200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 51500 46400 5 10 1 1 180 0 1
+refdes=C5
+T 50900 46200 5 10 0 0 90 0 1
+symversion=0.1
+T 51600 46600 5 10 1 1 180 0 1
+value=220p
+}
+C 51800 44900 1 90 0 capacitor-1.sym
+{
+T 51100 45100 5 10 0 0 90 0 1
+device=CAPACITOR
+T 51500 45300 5 10 1 1 180 0 1
+refdes=C4
+T 50900 45100 5 10 0 0 90 0 1
+symversion=0.1
+T 51600 45500 5 10 1 1 180 0 1
+value=220p
+}
+N 50800 46900 52300 46900 4
+N 52300 46700 52200 46700 4
+N 52200 46700 52200 44900 4
+N 50800 44900 52200 44900 4
+N 51600 45800 51600 46000 4
+C 51800 45500 1 0 0 gnd-1.sym
+N 51900 45800 51900 45900 4
+N 51900 45900 51600 45900 4
+C 51100 45500 1 90 0 capacitor-1.sym
+{
+T 50400 45700 5 10 0 0 90 0 1
+device=CAPACITOR
+T 50800 45900 5 10 1 1 180 0 1
+footprint=1812
+T 50200 45700 5 10 0 0 90 0 1
+symversion=0.1
+T 50900 46100 5 10 1 1 180 0 1
+value=22n
+}
+N 50900 45500 50900 44900 4
+N 50900 46400 50900 46900 4
+C 49900 46800 1 0 0 resistor-1.sym
+{
+T 50200 47200 5 10 0 0 0 0 1
+device=RESISTOR
+T 49900 46700 5 10 1 1 0 0 1
+refdes=R2
+T 50300 46700 5 10 1 1 0 0 1
+value=1k
+T 49900 46800 5 10 0 1 0 0 1
+footprint=0805
+}
+C 49900 44800 1 0 0 resistor-1.sym
+{
+T 50200 45200 5 10 0 0 0 0 1
+device=RESISTOR
+T 50000 45100 5 10 1 1 0 0 1
+refdes=R1
+T 50400 45100 5 10 1 1 0 0 1
+value=1k
+}
+N 42300 40800 42300 45500 4
+N 49900 44900 49500 44900 4
+{
+T 49700 44955 5 10 1 1 0 3 1
+netname=P1_A
+}
+N 48400 46900 49900 46900 4
+{
+T 48245 47050 5 10 1 1 90 3 1
+netname=P1_B
+}
+N 52300 47800 51500 47800 4
+{
+T 51950 47755 5 10 1 1 0 3 1
+netname=\_CS
+}
+N 52300 48000 51500 48000 4
+{
+T 51950 47955 5 10 1 1 0 3 1
+netname=SDI
+}
+N 52300 48200 51500 48200 4
+{
+T 51950 48155 5 10 1 1 0 3 1
+netname=SDO
+}
+N 52300 48400 51500 48400 4
+{
+T 51950 48355 5 10 1 1 0 3 1
+netname=SCLK
+}
+N 51500 48600 52300 48600 4
+C 52300 49600 1 180 0 xtal.sym
+{
+T 52205 49550 5 10 0 1 180 0 1
+device=XTAL
+T 52305 49551 5 10 0 1 180 0 1
+footprint=dip2
+T 52305 49150 5 10 1 1 180 0 1
+refdes=X1
+T 51500 49400 5 10 1 1 0 0 1
+value=4.096Mhz
+}
+C 53000 49700 1 0 0 capacitor-1.sym
+{
+T 53200 50400 5 10 0 0 0 0 1
+device=CAPACITOR
+T 53200 50000 5 10 1 1 0 0 1
+refdes=C1
+T 53200 50600 5 10 0 0 0 0 1
+symversion=0.1
+T 53000 49700 5 10 1 1 0 0 1
+value=100n
+}
+N 53900 49900 53900 49700 4
+N 52300 48800 52300 49200 4
+N 51500 48600 51500 49200 4
+C 50800 47300 1 90 0 capacitor-1.sym
+{
+T 50100 47500 5 10 0 0 90 0 1
+device=CAPACITOR
+T 50500 47700 5 10 1 1 180 0 1
+refdes=C7
+T 49900 47500 5 10 0 0 90 0 1
+symversion=0.1
+T 50600 47900 5 10 1 1 180 0 1
+footprint=0603
+}
+C 50800 48400 1 90 0 capacitor-1.sym
+{
+T 50100 48600 5 10 0 0 90 0 1
+device=CAPACITOR
+T 50500 48800 5 10 1 1 180 0 1
+refdes=C8
+T 49900 48600 5 10 0 0 90 0 1
+symversion=0.1
+T 50600 49000 5 10 1 1 180 0 1
+footprint=0603
+}
+C 50800 47900 1 0 0 gnd-1.sym
+N 49500 47200 52300 47200 4
+N 50600 47200 50600 47300 4
+N 52300 47400 51100 47400 4
+N 51100 47400 51100 49400 4
+N 49100 49400 51100 49400 4
+N 50600 49400 50600 49300 4
+N 50600 48200 50600 48400 4
+N 50900 48200 50900 48300 4
+N 50900 48300 50600 48300 4
+C 50100 48000 1 90 0 capacitor-1.sym
+{
+T 49400 48200 5 10 0 0 90 0 1
+device=CAPACITOR
+T 49800 48400 5 10 1 1 180 0 1
+refdes=C9
+T 49200 48200 5 10 0 0 90 0 1
+symversion=0.1
+T 49900 48600 5 10 1 1 180 0 1
+value=22n
+T 49200 48000 5 10 0 0 0 0 1
+footprint=1812
+}
+N 49900 48000 49900 47200 4
+N 49900 48900 49900 49400 4
+C 48600 47100 1 0 0 resistor-1.sym
+{
+T 48900 47500 5 10 0 0 0 0 1
+device=RESISTOR
+T 48900 47400 5 10 1 1 0 0 1
+refdes=R3
+T 49200 47300 5 10 0 1 0 0 1
+footprint=0805
+T 49100 47300 5 10 1 1 0 0 1
+value=1k
+}
+N 48400 46900 48400 47300 4
+N 48400 47200 48600 47200 4
+C 48500 47300 1 90 0 resistor-1.sym
+{
+T 48100 47600 5 10 0 0 90 0 1
+device=RESISTOR
+T 48600 47300 5 10 1 1 90 0 1
+refdes=R4
+T 48600 47700 5 10 1 1 90 0 1
+value=1k
+}
+C 48500 48500 1 90 0 resistor-1.sym
+{
+T 48100 48800 5 10 0 0 90 0 1
+device=RESISTOR
+T 48600 48500 5 10 1 1 90 0 1
+refdes=R5
+T 48600 48900 5 10 1 1 90 0 1
+value=2M
+}
+N 48400 49400 48400 49800 4
+{
+T 48350 49600 5 10 1 1 90 3 1
+netname=P2
+}
+N 48400 48200 48400 48500 4
+N 48400 48300 49100 48300 4
+N 49100 48300 49100 49400 4
+N 41400 49000 40400 49000 4
+{
+T 40900 48955 5 10 1 1 0 3 1
+netname=SDI
+}
+N 41400 49200 40400 49200 4
+{
+T 40900 49155 5 10 1 1 0 3 1
+netname=SDO
+}
+N 41400 48600 40400 48600 4
+{
+T 40900 48555 5 10 1 1 0 3 1
+netname=SCK
+}
+N 41400 48200 40400 48200 4
+{
+T 40900 48155 5 10 1 1 0 3 1
+netname=\_CS
+}
+N 41400 49400 40300 49400 4
+{
+T 40850 49455 5 10 1 1 0 3 1
+netname=LED
+}
+C 51600 43300 1 0 0 led-1.sym
+{
+T 52400 43900 5 10 0 0 0 0 1
+device=LED
+T 51900 43700 5 10 1 1 0 0 1
+refdes=LED?
+T 52400 44100 5 10 0 0 0 0 1
+symversion=0.1
+}
+C 50700 43400 1 0 0 resistor-1.sym
+{
+T 51000 43800 5 10 0 0 0 0 1
+device=RESISTOR
+T 50900 43700 5 10 1 1 0 0 1
+refdes=R7
+T 50900 43300 5 10 1 1 0 0 1
+value=220
+}
+N 50700 43500 50000 43500 4
+{
+T 50350 43555 5 10 1 1 0 3 1
+netname=LED
+}
+C 52600 43100 1 0 0 gnd-1.sym
+N 52700 43400 52700 43500 4
+N 52700 43500 52500 43500 4
+N 43200 44400 42300 44400 4
+C 46700 49700 1 0 0 switch-spst-1.sym
+{
+T 47100 50400 5 10 0 0 0 0 1
+device=SPST
+T 47000 50000 5 10 1 1 0 0 1
+refdes=S?
+}
+N 47500 49700 47500 47900 4
+N 47500 47900 47100 47900 4
+N 44000 49700 44000 49600 4
+C 44700 50600 1 0 0 generic-power.sym
+{
+T 44900 50850 5 10 1 1 0 3 1
+net=3.3Volt
+}
+C 45000 49700 1 90 0 resistor-1.sym
+{
+T 44600 50000 5 10 0 0 90 0 1
+device=RESISTOR
+T 44700 49900 5 10 1 1 90 0 1
+refdes=R8
+}
+N 44000 49200 44900 49200 4
+N 44900 49200 44900 49700 4
+N 44900 49700 46700 49700 4

qa/data/pcbnew/io/geda/minimal_test.pcb

@@ -0,0 +1,95 @@
+# release: pcb 20140316
+
+# To read pcb files, the pcb version (or the git source date) must be >= the file version
+FileVersion[20091103]
+
+PCB["minimal_test" 200.00mil 200.00mil]
+
+Grid[1000.000000 0.0000 0.0000 0]
+PolyArea[3100.006200]
+Thermal[0.500000]
+DRC[10.00mil 10.00mil 10.00mil 10.00mil 15.00mil 10.00mil]
+Flags("nameonpcb,uniquename,clearnew,snappin")
+Groups("1,c:2,s:3:4:5:6:7:8")
+Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"]
+
+Symbol[' ' 18.00mil]
+(
+)
+
+Element["" "0805" "R1" "10k" 5000 5000 -2000 -3000 0 100 ""]
+(
+	Attribute("device" "RESISTOR")
+	Pad[-393 -2755 393 -2755 2952 2000 3552 "1" "1" "square"]
+	Pad[-393 2755 393 2755 2952 2000 3552 "2" "2" "square"]
+	ElementLine [-1969 -3937 -1969 3937 800]
+	ElementLine [-1969 3937 1969 3937 800]
+	ElementLine [1969 3937 1969 -3937 800]
+	ElementLine [1969 -3937 -1969 -3937 800]
+
+	)
+
+Element["" "0603" "C1" "100nF" 15000 5000 -2000 -3000 0 100 ""]
+(
+	Attribute("device" "CAPACITOR")
+	Pad[-492 -2559 492 -2559 2952 2000 3552 "1" "1" "square"]
+	Pad[-492 2559 492 2559 2952 2000 3552 "2" "2" "square"]
+	ElementLine [-1574 -3543 -1574 3543 800]
+	ElementLine [-1574 3543 1574 3543 800]
+	ElementLine [1574 3543 1574 -3543 800]
+	ElementLine [1574 -3543 -1574 -3543 800]
+
+	)
+
+Via[10000 5000 3600 2000 0 2000 "" ""]
+
+Layer(1 "component")
+(
+	Line[5000 2245 10000 2245 1000 2000 "clearline"]
+	Line[10000 2245 10000 5000 1000 2000 "clearline"]
+)
+Layer(2 "solder")
+(
+	Line[10000 5000 15000 5000 1000 2000 "clearline"]
+	Line[15000 5000 15000 2441 1000 2000 "clearline"]
+)
+Layer(3 "GND")
+(
+)
+Layer(4 "power")
+(
+)
+Layer(5 "signal1")
+(
+)
+Layer(6 "signal2")
+(
+)
+Layer(7 "outline")
+(
+)
+Layer(8 "spare")
+(
+)
+Layer(9 "silk")
+(
+)
+Layer(10 "silk")
+(
+)
+NetList()
+(
+	Net("INPUT" "(unknown)")
+	(
+		Connect("R1-1")
+	)
+	Net("MID" "(unknown)")
+	(
+		Connect("R1-2")
+		Connect("C1-1")
+	)
+	Net("GND" "(unknown)")
+	(
+		Connect("C1-2")
+	)
+)

qa/data/pcbnew/io/geda/multilayer_test.pcb

@@ -0,0 +1,82 @@
+# release: pcb 20140316
+FileVersion[20091103]
+
+PCB["multilayer_test" 500.00mil 500.00mil]
+
+Grid[1000.000000 0.0000 0.0000 0]
+PolyArea[3100.006200]
+Thermal[0.500000]
+DRC[10.00mil 10.00mil 10.00mil 10.00mil 15.00mil 10.00mil]
+Flags("nameonpcb,uniquename,clearnew,snappin")
+Groups("1,c:2,s:3:4")
+Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"]
+
+Symbol[' ' 18.00mil]
+(
+)
+
+# Through-hole component
+Element["" "DIP8" "U1" "OPAMP" 25000 25000 -5000 -5000 0 100 ""]
+(
+	Pin[0 0 6000 3000 6600 2800 "1" "1" "square"]
+	Pin[10000 0 6000 3000 6600 2800 "2" "2" ""]
+	Pin[20000 0 6000 3000 6600 2800 "3" "3" ""]
+	Pin[30000 0 6000 3000 6600 2800 "4" "4" ""]
+	Pin[30000 30000 6000 3000 6600 2800 "5" "5" ""]
+	Pin[20000 30000 6000 3000 6600 2800 "6" "6" ""]
+	Pin[10000 30000 6000 3000 6600 2800 "7" "7" ""]
+	Pin[0 30000 6000 3000 6600 2800 "8" "8" ""]
+	ElementLine [-5000 -5000 35000 -5000 1000]
+	ElementLine [35000 -5000 35000 35000 1000]
+	ElementLine [35000 35000 -5000 35000 1000]
+	ElementLine [-5000 35000 -5000 -5000 1000]
+	)
+
+# Through-hole resistor
+Element["" "AXIAL300" "R1" "1k" 75000 25000 0 0 0 100 ""]
+(
+	Pin[0 0 6000 3000 6600 2800 "1" "1" "square"]
+	Pin[30000 0 6000 3000 6600 2800 "2" "2" ""]
+	ElementLine [5000 -2000 25000 -2000 1000]
+	ElementLine [25000 -2000 25000 2000 1000]
+	ElementLine [25000 2000 5000 2000 1000]
+	ElementLine [5000 2000 5000 -2000 1000]
+	ElementLine [0 0 5000 0 1000]
+	ElementLine [25000 0 30000 0 1000]
+	)
+
+Layer(1 "component")
+(
+	Line[25000 25000 75000 25000 1000 2000 "clearline"]
+)
+
+Layer(2 "solder")
+(
+	Line[55000 25000 75000 55000 1000 2000 "clearline"]
+)
+
+Layer(3 "inner1")
+(
+	Line[25000 55000 75000 55000 1000 2000 "clearline"]
+)
+
+Layer(4 "inner2")
+(
+	Line[55000 55000 25000 25000 1000 2000 "clearline"]
+)
+
+Via[55000 25000 6000 2000 0 2800 "" ""]
+
+NetList()
+(
+	Net("GND" "(unknown)")
+	(
+		Connect("U1-4")
+		Connect("R1-2")
+	)
+	Net("VCC" "(unknown)")
+	(
+		Connect("U1-8")
+		Connect("R1-1")
+	)
+)

qa/data/pcbnew/io/geda/non_geda.pcb

@@ -0,0 +1,7 @@
+# This is not a gEDA board file.
+# It has the right extension but lacks the required header.
+Some random content
+that is not a valid format.
+Version 1.0
+Width 100
+Height 200

qa/data/pcbnew/io/geda/onsolder_test.pcb

@@ -0,0 +1,38 @@
+# release: pcb 20140316
+FileVersion[20091103]
+
+PCB["onsolder_test" 200.00mil 200.00mil]
+
+Grid[1000.000000 0.0000 0.0000 0]
+PolyArea[3100.006200]
+Thermal[0.500000]
+DRC[10.00mil 10.00mil 10.00mil 10.00mil 15.00mil 10.00mil]
+Flags("nameonpcb,uniquename,clearnew,snappin")
+Groups("1,c:2,s")
+Styles["Signal,10.00mil,36.00mil,20.00mil,10.00mil:Power,25.00mil,60.00mil,35.00mil,10.00mil:Fat,40.00mil,60.00mil,35.00mil,10.00mil:Skinny,6.00mil,24.02mil,11.81mil,6.00mil"]
+
+Symbol[' ' 18.00mil]
+(
+)
+
+# Top-side resistor (no onsolder flag)
+Element["" "0805" "R1" "10k" 5000 5000 -2000 -3000 0 100 ""]
+(
+	Pad[-393 -2755 393 -2755 2952 2000 3552 "1" "1" "square"]
+	Pad[-393 2755 393 2755 2952 2000 3552 "2" "2" "square"]
+	ElementLine [-1969 -3937 -1969 3937 800]
+	ElementLine [-1969 3937 1969 3937 800]
+	ElementLine [1969 3937 1969 -3937 800]
+	ElementLine [1969 -3937 -1969 -3937 800]
+	)
+
+# Bottom-side capacitor (onsolder flag)
+Element["onsolder" "0603" "C1" "100nF" 15000 5000 -2000 -3000 0 100 ""]
+(
+	Pad[-295 -2067 295 -2067 2362 2000 2962 "1" "1" "square,onsolder"]
+	Pad[-295 2067 295 2067 2362 2000 2962 "2" "2" "square,onsolder"]
+	ElementLine [-1476 -2953 -1476 2953 800]
+	ElementLine [-1476 2953 1476 2953 800]
+	ElementLine [1476 2953 1476 -2953 800]
+	ElementLine [1476 -2953 -1476 -2953 800]
+	)