board area fixes (jpc)

This commit is contained in:
jean-pierre charras
2025-06-19 18:26:39 +02:00
parent ea12df80be
commit 01e67d78d6
12 changed files with 39 additions and 24 deletions
+1 -1
View File
@@ -152,7 +152,7 @@ wxString LayerName( int aLayer )
case LAYER_SELECT_OVERLAY: return _( "Selection highlight" );
case LAYER_LOCKED_ITEM_SHADOW: return _( "Locked item shadow" );
case LAYER_CONFLICTS_SHADOW: return _( "Courtyard collision shadow" );
case LAYER_BOARD_OUTLINE: return _( "Board outline" );
case LAYER_BOARD_OUTLINE_AREA: return _( "Board outline area" );
case NETNAMES_LAYER_ID_START: return _( "Track net names" );
case LAYER_PAD_NETNAMES: return _( "Pad net names" );
case LAYER_VIA_NETNAMES: return _( "Via net names" );
+2 -2
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@@ -171,7 +171,7 @@ static const std::map<int, COLOR4D> s_defaultTheme =
{ LAYER_VIA_HOLEWALLS, CSS_COLOR( 236, 236, 236, 1 ) },
{ LAYER_DRAWINGSHEET, CSS_COLOR( 200, 114, 171, 1 ) },
{ LAYER_PAGE_LIMITS, CSS_COLOR( 132, 132, 132, 1 ) },
{ LAYER_BOARD_OUTLINE, CSS_COLOR( 109, 106, 105,1 ) },
{ LAYER_BOARD_OUTLINE_AREA, CSS_COLOR( 50, 50, 50, 1 ) },
{ NETNAMES_LAYER_ID_START, CSS_COLOR( 255, 255, 255, 0.7 ) },
{ LAYER_PAD_NETNAMES, CSS_COLOR( 255, 255, 255, 0.9 ) },
{ LAYER_VIA_NETNAMES, CSS_COLOR( 50, 50, 50, 0.9 ) },
@@ -446,7 +446,7 @@ static const std::map<int, COLOR4D> s_classicTheme =
{ LAYER_VIA_HOLEWALLS, COLOR4D( WHITE ) },
{ LAYER_DRAWINGSHEET, COLOR4D( DARKRED ) },
{ LAYER_PAGE_LIMITS, COLOR4D( DARKGRAY) },
{ LAYER_BOARD_OUTLINE, CSS_COLOR( 109, 106, 105,1 ) },
{ LAYER_BOARD_OUTLINE_AREA, CSS_COLOR( 50, 50, 50, 1 ) },
{ NETNAMES_LAYER_ID_START, CSS_COLOR( 255, 255, 255, 0.7 ) },
{ LAYER_PAD_NETNAMES, CSS_COLOR( 255, 255, 255, 0.9 ) },
{ LAYER_VIA_NETNAMES, CSS_COLOR( 50, 50, 50, 0.9 ) },
+1 -1
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@@ -138,7 +138,7 @@ COLOR_SETTINGS::COLOR_SETTINGS( const wxString& aFilename, bool aAbsolutePath )
CLR( "board.via_hole_walls", LAYER_VIA_HOLEWALLS );
CLR( "board.worksheet", LAYER_DRAWINGSHEET );
CLR( "board.page_limits", LAYER_PAGE_LIMITS );
CLR( "board.outline", LAYER_BOARD_OUTLINE );
CLR( "board.outline_area", LAYER_BOARD_OUTLINE_AREA );
CLR( "board.track_net_names", NETNAMES_LAYER_ID_START );
CLR( "board.pad_net_names", LAYER_PAD_NETNAMES );
CLR( "board.via_net_names", LAYER_VIA_NETNAMES );
@@ -499,7 +499,8 @@ SCH_EASYEDAPRO_PARSER::ParseSymbol( const std::vector<nlohmann::json>& aLines,
std::vector<double> points = line.at( 2 );
wxString styleStr = line.at( 3 );
auto shape = std::make_unique<SCH_SHAPE>( SHAPE_T::BEZIER, LAYER_DEVICE );
std::unique_ptr<SCH_SHAPE> shape =
std::make_unique<SCH_SHAPE>( SHAPE_T::BEZIER, LAYER_DEVICE );
for( size_t i = 1; i < points.size(); i += 2 )
{
+1 -1
View File
@@ -314,7 +314,7 @@ enum GAL_LAYER_ID: int
LAYER_DRC_SHAPE1 = GAL_LAYER_ID_START + 42, ///< Custom shape for DRC marker.
LAYER_DRC_SHAPE2 = GAL_LAYER_ID_START + 43, ///< Custom shape for DRC marker.
LAYER_BOARD_OUTLINE = GAL_LAYER_ID_START + 44, ///< PCB board outline
LAYER_BOARD_OUTLINE_AREA = GAL_LAYER_ID_START + 44, ///< PCB board outline
// Add layers below this point that do not have visibility controls, so don't need explicit
// enum values
+5 -4
View File
@@ -3114,11 +3114,12 @@ bool BOARD::operator==( const BOARD_ITEM& aItem ) const
void BOARD::UpdateBoardOutline()
{
SHAPE_POLY_SET outline;
bool has_outline = GetBoardPolygonOutlines( m_boardOutline->GetOutline() );
m_boardOutline->GetOutline().RemoveAllContours();
if( !has_outline )
m_boardOutline->GetOutline().RemoveAllContours();
bool has_outline = GetBoardPolygonOutlines( m_boardOutline->GetOutline() );
if( has_outline )
m_boardOutline->GetOutline().Fracture();
}
+6 -2
View File
@@ -521,8 +521,12 @@ void BOARD_COMMIT::Push( const wxString& aMessage, int aCommitFlags )
if( PCB_BOARD_OUTLINE* outline = board->BoardOutline() )
{
board->UpdateBoardOutline();
view->Update( outline );
}
if( view->HasItem( outline ) )
view->Update( outline );
else
view->Add( outline );
}
}
if( PCBNEW_SETTINGS* cfg = GetAppSettings<PCBNEW_SETTINGS>( "pcbnew" ) )
@@ -712,6 +712,7 @@ PANEL_PCBNEW_COLOR_SETTINGS::PANEL_PCBNEW_COLOR_SETTINGS( wxWindow* aParent, BOA
// These layers are not in GAL_LAYER_ID_START ... GAL_LAYER_ID_BITMASK_END
m_validLayers.push_back( LAYER_LOCKED_ITEM_SHADOW );
m_validLayers.push_back( LAYER_CONFLICTS_SHADOW );
m_validLayers.push_back( LAYER_BOARD_OUTLINE_AREA );
m_validLayers.push_back( LAYER_PAGE_LIMITS );
m_validLayers.push_back( LAYER_DRC_WARNING );
m_validLayers.push_back( LAYER_DRC_EXCLUSION );
+11 -7
View File
@@ -58,22 +58,26 @@ PCB_BOARD_OUTLINE::~PCB_BOARD_OUTLINE()
{
}
void PCB_BOARD_OUTLINE::ViewGetLayers( int aLayers[], int& aCount ) const
std::vector<int> PCB_BOARD_OUTLINE::ViewGetLayers() const
{
aCount = 1;
aLayers[0] = LAYER_BOARD_OUTLINE;
std::vector<int> layers { LAYER_BOARD_OUTLINE_AREA };
return layers;
}
const BOX2I PCB_BOARD_OUTLINE::GetBoundingBox() const
{
return m_outlines.BBox();
}
PCB_LAYER_ID PCB_BOARD_OUTLINE::GetLayer() const
{
return UNDEFINED_LAYER;
}
LSET PCB_BOARD_OUTLINE::GetLayerSet() const
{
return {};
@@ -87,15 +91,15 @@ bool PCB_BOARD_OUTLINE::IsOnLayer( PCB_LAYER_ID aLayer ) const
double PCB_BOARD_OUTLINE::Similarity( const BOARD_ITEM& aItem ) const
{
if( const PCB_BOARD_OUTLINE* outline = dynamic_cast<const PCB_BOARD_OUTLINE*>( &aItem ) )
if( aItem.Type() == KICAD_T::PCB_BOARD_OUTLINE_T )
{
if( m_parent == aItem.GetParent() )
return 1;
return 1.0;
return 0.5;
}
return {};
return 0.0;
}
bool PCB_BOARD_OUTLINE::operator==( const BOARD_ITEM& aItem ) const
@@ -123,7 +127,7 @@ wxString PCB_BOARD_OUTLINE::GetClass() const
void PCB_BOARD_OUTLINE::Show( int nestLevel, std::ostream& os ) const
{
NestedSpace( nestLevel, os ) << '<' << GetClass().Lower().mb_str() << wxS( ">\n" );
NestedSpace( nestLevel, os ) << '<' << GetClass().Lower().mb_str() << ">\n";
}
#endif
+1 -1
View File
@@ -46,7 +46,7 @@ public:
SHAPE_POLY_SET& GetOutline() { return m_outlines; }
void ViewGetLayers( int aLayers[], int& aCount ) const override;
std::vector<int> ViewGetLayers() const override;
const BOX2I GetBoundingBox() const override;
+5 -2
View File
@@ -356,6 +356,8 @@ const int GAL_LAYER_ORDER[] =
BITMAP_LAYER_FOR( B_CrtYd ),
BITMAP_LAYER_FOR( B_Fab ),
LAYER_BOARD_OUTLINE_AREA,
LAYER_DRAWINGSHEET
};
@@ -588,7 +590,7 @@ void PCB_DRAW_PANEL_GAL::SetTopLayer( PCB_LAYER_ID aLayer )
m_view->SetTopLayer( PAD_COPPER_LAYER_FOR( layer ) );
m_view->SetTopLayer( VIA_COPPER_LAYER_FOR( layer ) );
m_view->SetTopLayer( CLEARANCE_LAYER_FOR( layer ) );
}
}
}
// Move the active layer to the top of the stack but below all the overlay layers
@@ -670,7 +672,7 @@ void PCB_DRAW_PANEL_GAL::SyncLayersVisibility( const BOARD* aBoard )
m_view->SetLayerVisible( LAYER_SELECT_OVERLAY, true );
m_view->SetLayerVisible( LAYER_RATSNEST, true );
m_view->SetLayerVisible( LAYER_MARKER_SHADOWS, true );
m_view->SetLayerVisible( LAYER_BOARD_OUTLINE, true );
m_view->SetLayerVisible( LAYER_BOARD_OUTLINE_AREA, true );
m_view->SetLayerVisible( LAYER_DRC_SHAPE1, true );
m_view->SetLayerVisible( LAYER_DRC_SHAPE2, true );
}
@@ -843,6 +845,7 @@ void PCB_DRAW_PANEL_GAL::setDefaultLayerDeps()
m_view->SetLayerDisplayOnly( LAYER_LOCKED_ITEM_SHADOW );
m_view->SetLayerDisplayOnly( LAYER_CONFLICTS_SHADOW );
m_view->SetLayerDisplayOnly( LAYER_BOARD_OUTLINE_AREA );
// Some more required layers settings
m_view->SetRequired( LAYER_PAD_NETNAMES, LAYER_PADS );
+3 -2
View File
@@ -3014,8 +3014,9 @@ void PCB_PAINTER::draw( const PCB_BOARD_OUTLINE* aBoardOutline, int aLayer )
if( !aBoardOutline->HasOutline() )
return;
GAL_SCOPED_ATTRS scopedAttrs( *m_gal, GAL_SCOPED_ATTRS::ALL_ATTRS );
m_gal->Save();
m_gal->PushDepth();
const COLOR4D& outlineColor = m_pcbSettings.GetColor( aBoardOutline, aLayer );
m_gal->SetFillColor( outlineColor );
m_gal->AdvanceDepth();
@@ -3023,7 +3024,7 @@ void PCB_PAINTER::draw( const PCB_BOARD_OUTLINE* aBoardOutline, int aLayer )
m_gal->SetIsFill( true );
m_gal->SetIsStroke( false );
m_gal->DrawPolygon( aBoardOutline->GetOutline() );
m_gal->PopDepth();
m_gal->Restore();
}