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fix(audio): error handling ES8388 + define DAC_CTL27

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clement
2026-06-19 08:57:06 +02:00
parent e14c912dac
commit f452387d92
1 changed files with 23 additions and 13 deletions
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components/hal_es8388/es8388.c
+23 -13
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@@ -63,6 +63,7 @@ static i2c_master_dev_handle_t s_es_dev = NULL;
#define ES8388_DAC_CTL24 0x2E /* DACCONTROL24 — LOUT1VOL (OUT1 left volume) */
#define ES8388_DAC_CTL25 0x2F /* DACCONTROL25 — ROUT1VOL (OUT1 right volume) */
#define ES8388_DAC_CTL26 0x30 /* DACCONTROL26 — LOUT2VOL (OUT2 left volume) */
#define ES8388_DAC_CTL27 0x31 /* DACCONTROL27 — ROUT2VOL (OUT2 right volume) */
/* Volume register: 0x00=0dB (max), 0x21=-33dB step per 1.5dB, 0x24=mute. */
#define ES8388_VOL_MAX 0x00
@@ -175,7 +176,7 @@ esp_err_t es8388_init(void)
* - ADCCONTROL4 (0x0C) = 0x0C: I2S Philips 16-bit word length
* - ADCCONTROL5 (0x0D) = 0x02: ADCFsMode SINGLE SPEED RATIO=256 (16kHz@MCLK 4.096MHz)
* - ADCCONTROL8/9 (0x10/0x11) = 0x00: ADC digital volume 0dB */
if (i2c_write_reg(ES8388_ADC_CTL1, 0x88) != ESP_OK) return ESP_FAIL; /* MIC PGA +24dB L+R — the SLIC handset mic is QUIET (~2-5% FS at +12dB); +24dB lifts speech above the capture VAD onset. The old "+24dB too hot" note was an artifact of the broken ADC (pre-DLL-fix); measured clean at ~5% peak now. */
if (i2c_write_reg(ES8388_ADC_CTL1, 0x88) != ESP_OK) return ESP_FAIL; /* 0x88 = MICAMPL/MICAMPR=0b10 → MIC PGA +12 dB L+R — the SLIC handset mic is QUIET; +12 dB lifts speech above the capture VAD onset without clipping (measured clean at ~5% peak post DLL-fix). */
/* ADCCONTROL2 (0x0A): input select. The K50835F SLIC handset transmit audio is
* wired to LIN2/RIN2 on this bench — PROVEN: speech captured (ACrms 196, crest 10.3)
* on 0x50, vs DC-only floating offset on 0x00 (LIN1). */
@@ -240,12 +241,18 @@ esp_err_t es8388_init(void)
/* Verify key register values to confirm ADC path is configured correctly. */
uint8_t ctl1=0, adcpwr=0, adcinsel=0, dacctl21=0, chippower=0, adcctl3=0;
es8388_read_reg(ES8388_CHIP_CTL1, &ctl1);
es8388_read_reg(ES8388_ADC_POWER, &adcpwr);
es8388_read_reg(ES8388_ADC_CTL2, &adcinsel); /* ADCCONTROL2 = input sel (0x50=LIN2) */
es8388_read_reg(ES8388_ADC_CTL3, &adcctl3); /* ADCCONTROL3 = DS filter (0x02) */
es8388_read_reg(ES8388_DAC_CTL21, &dacctl21); /* DACCONTROL21 = ADC+DAC LRCK sync (0xC0) */
es8388_read_reg(ES8388_CHIP_POWER, &chippower);
if (es8388_read_reg(ES8388_CHIP_CTL1, &ctl1) != ESP_OK)
ESP_LOGW(TAG, "read CHIP_CTL1 failed");
if (es8388_read_reg(ES8388_ADC_POWER, &adcpwr) != ESP_OK)
ESP_LOGW(TAG, "read ADC_POWER failed");
if (es8388_read_reg(ES8388_ADC_CTL2, &adcinsel) != ESP_OK) /* ADCCONTROL2 = input sel (0x50=LIN2) */
ESP_LOGW(TAG, "read ADC_CTL2 failed");
if (es8388_read_reg(ES8388_ADC_CTL3, &adcctl3) != ESP_OK) /* ADCCONTROL3 = DS filter (0x02) */
ESP_LOGW(TAG, "read ADC_CTL3 failed");
if (es8388_read_reg(ES8388_DAC_CTL21, &dacctl21) != ESP_OK) /* DACCONTROL21 = ADC+DAC LRCK sync (0xC0) */
ESP_LOGW(TAG, "read DAC_CTL21 failed");
if (es8388_read_reg(ES8388_CHIP_POWER, &chippower) != ESP_OK)
ESP_LOGW(TAG, "read CHIP_POWER failed");
ESP_LOGI(TAG, "ES8388 regs: CTL1=0x%02X ADCPWR=0x%02X ADCINSEL=0x%02X ADCCTL3=0x%02X DACCTL21=0x%02X CHIPPOWER=0x%02X",
ctl1, adcpwr, adcinsel, adcctl3, dacctl21, chippower);
ESP_LOGI(TAG, "ES8388 init OK — PA enabled, DAC @ 0dB, ADC PGA +12dB, input=LIN2/RIN2 (SLIC handset), DACCTL21=0x80");
@@ -264,11 +271,13 @@ esp_err_t es8388_set_volume(uint8_t vol)
uint8_t reg_val = (uint8_t)((int)vol * 0x21 / 100);
if (reg_val > 0x21) reg_val = 0x21;
ESP_LOGI(TAG, "set_volume: %d%% -> reg=0x%02X (0x21=max,0dB)", vol, reg_val);
esp_err_t r = ESP_OK;
r |= i2c_write_reg(ES8388_DAC_CTL24, reg_val); /* OUT1 L volume */
r |= i2c_write_reg(ES8388_DAC_CTL25, reg_val); /* OUT1 R volume */
r |= i2c_write_reg(ES8388_DAC_CTL26, reg_val); /* OUT2 L volume */
r |= i2c_write_reg(0x31, reg_val); /* OUT2 R volume (DACCONTROL27) */
esp_err_t r = i2c_write_reg(ES8388_DAC_CTL24, reg_val); /* OUT1 L volume */
if (r != ESP_OK) return r;
r = i2c_write_reg(ES8388_DAC_CTL25, reg_val); /* OUT1 R volume */
if (r != ESP_OK) return r;
r = i2c_write_reg(ES8388_DAC_CTL26, reg_val); /* OUT2 L volume */
if (r != ESP_OK) return r;
r = i2c_write_reg(ES8388_DAC_CTL27, reg_val); /* OUT2 R volume */
return r;
}
@@ -281,7 +290,8 @@ esp_err_t es8388_set_dac_volume(uint8_t atten)
if (atten > 0xC0) atten = 0xC0;
ESP_LOGI(TAG, "set_dac_volume: atten=0x%02X (-%.1f dB)", atten, atten * 0.5f);
esp_err_t r = i2c_write_reg(ES8388_DAC_CTL4, atten);
r |= i2c_write_reg(ES8388_DAC_CTL5, atten);
if (r != ESP_OK) return r;
r = i2c_write_reg(ES8388_DAC_CTL5, atten);
return r;
}