Reapply "Setting DSE=3 on output pins yeilded extra 7% LED overclock. Also found PJRC forum references for this."

This reverts commit 5a849e7ed1.

ObjectFLED.h

@@ -41,6 +41,11 @@
 #include <WProgram.h>
 #include "DMAChannel.h"
 
+//Experimentally found DSE=3, SPEED=0 gave best LED overclocking
+//boot defaults DSE=6, SPEED=2.
+#define OUTPUT_PAD_DSE		3		//Legal values 0-7
+#define OUTPUT_PAD_SPEED	0		//Legal values 0-3
+
 // Ordinary RGB data is converted to GPIO bitmasks on-the-fly using
 // a transmit buffer sized for 2 DMA transfers.  The larger this setting,
 // the more interrupt latency OctoWS2811 can tolerate, but the transmit
@@ -148,8 +153,8 @@ private:
 	uint8_t serpNumber;
 	float OC_FACTOR = 1.0;					//used to reduce period of LED output
 	uint16_t TH_TL = 1250;					//nS- period of LED output
-	uint16_t T0H = TH_TL / 3.0;				//nS- duration of T0H
-	uint16_t T1H = TH_TL * 2.0 / 3.0;		//nS- duration of T1H
+	uint16_t T0H = TH_TL / 3;				//nS- duration of T0H
+	uint16_t T1H = TH_TL * 2 / 3;			//nS- duration of T1H
 	uint16_t LATCH_DELAY = 75;				//uS time to hold output low for LED latch.
 
 	//for show context switch

OjectFLED.cpp

@@ -154,6 +154,10 @@ void ObjectFLED::begin(void) {
 		pin_offset[i] = offset;		//static/isr
 		uint32_t mask = 1 << bit;	//mask32 = bit set @position in GPIO DR
 		bitmask[offset] |= mask;	//bitmask32[0..3] = collective pin bit masks for each GPIO DR
+		//bit7:6 SPEED; bit 5:3 DSE; bit0 SRE  (default SPEED = 0b10; def. DSE = 0b110)
+		*portControlRegister(pin) &= ~0xF9;		//clear SPEED, DSE, SRE
+		*portControlRegister(pin) |= ((OUTPUT_PAD_SPEED & 0x3) << 6) | \
+			((OUTPUT_PAD_DSE & 0x7) << 3);	//DSE = 0b011 for LED overclock
 		//clear pin bit in IOMUX_GPR26 to map GPIO6-9 to GPIO1-4 for DMA 
 		*(&IOMUXC_GPR_GPR26 + offset) &= ~mask;		
 		*standard_gpio_addr(portModeRegister(pin)) |= mask;		//GDIR? bit flag set output mode