Clément SAILLANT
d7ffbf14cf
- Introduced new documentation for design reviews (DR0/DR1) and release rituals. - Created templates for Architecture Decision Records (ADR), Design Reviews, Playtest Reports, and Validation Plans. - Established workflows for consulting, creative processes, systems engineering, R&D spikes, and compliance/QA. - Implemented GitHub Actions workflows for firmware and hardware CI with required checks strategy. - Added setup script for repository configuration, including label creation and branch protection. - Developed installation script for Kill_LIFE with system updates and environment setup.
45 lines
1.4 KiB
Markdown
45 lines
1.4 KiB
Markdown
# Workflow — Bureau d’études / Ingénierie système (HW/FW)
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## But
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Produire une architecture end‑to‑end : interfaces, budgets, risques, plan de validation, puis backlog.
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## Phases
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### 1) Requirements engineering (requirements → spec)
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- Livrables : RFC2119 + NFR + AC + matrice traçabilité (AC → tests)
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- Label : `ai:spec`
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### 2) Architecture système (design → ADR)
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- Livrables : diagrammes blocs, interfaces, budgets (power/memory/latency), modes de panne, ADR
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- Label : `ai:plan`
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### 3) Design review (DR0/DR1)
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- DR0 : cohérence + risques (pas de “dead ends”)
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- DR1 : budgets + plan de validation + BOM
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- Livrables : checklist review + décisions (ADR)
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- Labels : `ai:plan` puis `ai:qa` (si tu veux injecter la test matrix)
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### 4) Backlog (WBS)
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- Livrables : epics/stories, tâches, critères d’acceptation
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- Label : `ai:tasks`
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### 5) Exécution (impl + tests)
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- Firmware : drivers + tasks + logs + watchdog
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- Hardware : schéma/PCB + DRC/ERC
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- Labels : `ai:impl` / `ai:qa`
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## Gates
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- Budgets explicités (power, mémoire, latence)
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- Plan de validation (unit/integration/HIL/endurance)
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- Scope guard :
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- `ai:spec` doit rester dans `specs/` + `docs/`
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- `ai:impl` ne touche pas aux workflows
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## Evidence pack
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Voir `docs/evidence/evidence_pack.md` + exports (KiCad + BOM + logs CI).
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## Mode “BE” recommandé (cadence)
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- Triage hebdo (30 min)
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- DR0 et DR1 (60–90 min)
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- ADR obligatoire pour : MCU/RTOS, bus, power architecture, radio stack
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