Claude Worker claude2
e1a116d0f5
Custom ESP32-WROOM-32E + Si3210 SLIC board replacing the ESP32-A1S dev kit (final PLIP target, RJ9 handset). Generated via tools/ gen_si3210_lib.py (symbol + QFN-38 footprint), gen_schematic.py (parses standard KiCad libs, 45 instances, 157 global labels on pin ends) and gen_pcb.py (58x38mm outline, 41 footprints placed per the plan, nets assigned, unrouted). ERC: 0 violations. Schematic follows the spec GPIO map and the plan's passive network. PCB placed not routed (Freerouting + DRC + gerbers remain — see README). BOM in JLCPCB format; CP2102N/transformer/RJ9 LCSC parts marked TBD. WARNINGS (README): the Si3210 -72V DC-DC stage is simplified and must be checked against the Skyworks datasheet/AN35 before fab; line protection is minimal; human review required before ordering.
113 lines
2.7 KiB
Plaintext
113 lines
2.7 KiB
Plaintext
{
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"board": {
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"3dviewports": [],
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"design_settings": {
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"defaults": {},
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"diff_pair_dimensions": [],
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"drc_exclusions": [],
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"rules": {
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"min_clearance": 0.15,
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"min_track_width": 0.2,
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"min_via_diameter": 0.6,
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"min_through_hole_diameter": 0.3
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},
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"track_widths": [0.2, 0.3, 0.4],
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"via_dimensions": [
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{ "diameter": 0.6, "drill": 0.3 }
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]
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},
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"layer_presets": [],
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"viewports": []
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},
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"boards": [],
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"cvpcb": {
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"equivalence_files": []
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},
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"libraries": {
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"pinned_footprint_libs": ["Si3210"],
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"pinned_symbol_libs": ["Si3210"]
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},
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"meta": {
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"filename": "plip-telephone.kicad_pro",
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"version": 3
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},
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"net_settings": {
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"classes": [
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{
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"bus_width": 12,
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"clearance": 0.15,
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"diff_pair_gap": 0.25,
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"diff_pair_via_gap": 0.25,
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"diff_pair_width": 0.2,
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"line_style": 0,
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"microvia_diameter": 0.3,
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"microvia_drill": 0.1,
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"name": "Default",
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"pcb_color": "rgba(0, 0, 0, 0.000)",
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"schematic_color": "rgba(0, 0, 0, 0.000)",
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"track_width": 0.2,
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"via_diameter": 0.6,
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"via_drill": 0.3,
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"wire_width": 6
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}
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],
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"meta": {
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"version": 4
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}
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},
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"pcbnew": {
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"last_paths": {
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"gencad": "",
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"idf": "",
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"netlist": "",
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"plot": "gerbers/",
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"pos_files": "jlcpcb/",
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"specctra_dsn": "",
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"step": "",
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"svg": "",
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"vrml": ""
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},
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"page_layout_descr_file": ""
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},
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"schematic": {
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"annotate_start_num": 0,
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"bom_export_filename": "",
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"drawing": {
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"dashed_lines_dash_length_ratio": 12.0,
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"dashed_lines_gap_length_ratio": 3.0,
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"default_line_thickness": 6.0,
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"default_text_size": 50.0,
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"field_names": [],
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"intersheets_ref_own_page": false,
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"intersheets_ref_prefix": "",
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"intersheets_ref_short": false,
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"intersheets_ref_show": false,
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"intersheets_ref_suffix": "",
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"junction_size_choice": 3,
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"label_size_ratio": 0.375,
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"pin_symbol_size": 25.0,
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"text_offset_ratio": 0.15
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},
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"legacy_lib_dir": "",
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"legacy_lib_list": [],
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"meta": {
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"version": 1
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},
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"net_format_name": "",
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"page_layout_descr_file": "",
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"plot_directory": "",
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"spice_current_sheet_as_root": false,
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"spice_external_command": "spice \"%I\"",
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"spice_model_current_sheet_as_root": true,
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"spice_save_all_currents": false,
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"spice_save_all_dissipations": false,
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"spice_save_all_voltages": false,
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"subpart_first_id": 65,
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"subpart_id_separator": 0
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},
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"sheets": [
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["5a3c9d2e-1f47-4b8a-9c61-7e2d84f0b3a1", "Racine"]
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],
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"text_variables": {}
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}
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