Seth Hillbrand
ba54c640ab
When choosing the shorted net name, ensure that we are alphabetically sorted for vectors to keep a consistent name Fixes https://gitlab.com/kicad/code/kicad/-/issues/18606
124 lines
4.4 KiB
C++
124 lines
4.4 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright The KiCad Developers, see AUTHORS.TXT for contributors.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 3
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* https://www.gnu.org/licenses/gpl-3.0.en.html
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* or you may search the http://www.gnu.org website for the version 32 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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/**
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* @file test_bus_net_name_determinism.cpp
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* Test for issue 18606: net name of shorted nets should be deterministic
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* when part of a higher-level bus definition.
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*
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* When multiple nets from a bus (e.g., A0, A1, A2, A3 from bus A[0..3]) are
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* shorted together, the resulting combined net name should be deterministically
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* chosen (alphabetically first: A0).
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*/
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#include <qa_utils/wx_utils/unit_test_utils.h>
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#include <schematic_utils/schematic_file_util.h>
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#include <connection_graph.h>
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#include <schematic.h>
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#include <sch_sheet.h>
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#include <sch_screen.h>
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#include <sch_symbol.h>
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#include <sch_pin.h>
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#include <settings/settings_manager.h>
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#include <locale_io.h>
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struct BUS_NET_NAME_DETERMINISM_FIXTURE
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{
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BUS_NET_NAME_DETERMINISM_FIXTURE()
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{ }
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SETTINGS_MANAGER m_settingsManager;
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std::unique_ptr<SCHEMATIC> m_schematic;
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};
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/**
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* Test that when bus member nets (A0, A1, A2, A3) are shorted together,
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* the resulting net name is deterministic (should be "A0" - alphabetically first).
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*
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* The test schematic has:
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* - Parent sheet with bus A[0..3] connected to a hierarchical sheet
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* - Child sheet with hierarchical label A[0..3], bus entries to A0, A1, A2, A3
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* - All four nets (A0, A1, A2, A3) are shorted together via junctions
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* - A resistor R201 is connected to the shorted nets
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*/
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BOOST_FIXTURE_TEST_CASE( ShortedBusNetsHaveDeterministicName, BUS_NET_NAME_DETERMINISM_FIXTURE )
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{
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LOCALE_IO dummy;
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// Load the test schematic multiple times to verify determinism
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for( int iteration = 0; iteration < 3; ++iteration )
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{
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KI_TEST::LoadSchematic( m_settingsManager, "issue18606/issue18606", m_schematic );
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SCH_SHEET_LIST sheets = m_schematic->BuildSheetListSortedByPageNumbers();
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// Find the resistor R201 in the child sheet and check its pin's net name
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wxString foundNetName;
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bool foundResistor = false;
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for( const SCH_SHEET_PATH& path : sheets )
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{
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SCH_SCREEN* screen = path.LastScreen();
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for( SCH_ITEM* item : screen->Items().OfType( SCH_SYMBOL_T ) )
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{
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SCH_SYMBOL* symbol = static_cast<SCH_SYMBOL*>( item );
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if( symbol->GetRef( &path ) == "R201" )
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{
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foundResistor = true;
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for( SCH_PIN* pin : symbol->GetPins( &path ) )
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{
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SCH_CONNECTION* conn = pin->Connection( &path );
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if( conn )
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{
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foundNetName = conn->Name();
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break;
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}
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}
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break;
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}
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}
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if( foundResistor )
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break;
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}
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BOOST_CHECK_MESSAGE( foundResistor, "R201 should be found in the schematic" );
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// The net name should be deterministic - alphabetically "A0" should win
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// when A0, A1, A2, A3 are shorted together.
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// The path is "/" (not "/test/") because the net name is inherited from the
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// parent sheet's bus A[0..3] during hierarchical propagation.
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BOOST_CHECK_MESSAGE( foundNetName == "/A0",
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"Net name should be '/A0' (alphabetically first bus member), "
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"but got '" << foundNetName.ToStdString() << "' on iteration "
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<< iteration );
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}
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}
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