Damjan Prerad
034af9d217
Overlapping closed cutouts on Edge.Cuts were not reported in DRC and 3D view of these overlapped coutouts was not renderd correctly. This change adds explicit DRC detection for overlapping closed Edge.Cuts contours and footprint Edge.Cuts contours. Fixes https://gitlab.com/kicad/code/kicad/-/work_items/21829
489 lines
19 KiB
C++
489 lines
19 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright The KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <pcb_shape.h>
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#include <pcb_board_outline.h>
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#include <board_design_settings.h>
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#include <footprint.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <geometry/seg.h>
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#include <geometry/shape_segment.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <drc/drc_rtree.h>
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/*
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Board edge clearance test. Checks all items for their mechanical clearances against the board
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edge.
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Errors generated:
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- DRCE_EDGE_CLEARANCE
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- DRCE_SILK_EDGE_CLEARANCE
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*/
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enum SILK_DISPOSITION {
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UNKNOWN = 0,
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ON_BOARD,
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OFF_BOARD,
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CROSSES_EDGE
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};
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class DRC_TEST_PROVIDER_EDGE_CLEARANCE : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_EDGE_CLEARANCE () :
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DRC_TEST_PROVIDER(),
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m_largestEdgeClearance( 0 ),
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m_epsilon( 0 )
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{}
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virtual ~DRC_TEST_PROVIDER_EDGE_CLEARANCE() = default;
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virtual bool Run() override;
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virtual const wxString GetName() const override { return wxT( "edge_clearance" ); }
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private:
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void resolveSilkDisposition( BOARD_ITEM* aItem, const SHAPE* aItemShape, const SHAPE_POLY_SET& aBoardOutline );
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bool testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* other, DRC_CONSTRAINT_T aConstraintType,
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PCB_DRC_CODE aErrorCode );
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private:
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std::vector<PAD*> m_castellatedPads;
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int m_largestEdgeClearance;
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int m_epsilon;
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DRC_RTREE m_edgesTree;
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std::map<BOARD_ITEM*, SILK_DISPOSITION> m_silkDisposition;
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};
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void DRC_TEST_PROVIDER_EDGE_CLEARANCE::resolveSilkDisposition( BOARD_ITEM* aItem, const SHAPE* aItemShape,
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const SHAPE_POLY_SET& aBoardOutline )
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{
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SILK_DISPOSITION disposition = UNKNOWN;
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if( aItemShape->Type() == SH_COMPOUND )
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{
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const SHAPE_COMPOUND* compound = static_cast<const SHAPE_COMPOUND*>( aItemShape );
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for( const SHAPE* elem : compound->Shapes() )
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{
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SILK_DISPOSITION elem_disposition = aBoardOutline.Contains( elem->Centre() ) ? ON_BOARD : OFF_BOARD;
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if( disposition == UNKNOWN )
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{
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disposition = elem_disposition;
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}
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else if( disposition != elem_disposition )
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{
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disposition = CROSSES_EDGE;
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break;
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}
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}
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}
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else
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{
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disposition = aBoardOutline.Contains( aItemShape->Centre() ) ? ON_BOARD : OFF_BOARD;
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}
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m_silkDisposition[aItem] = disposition;
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if( disposition == CROSSES_EDGE )
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{
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BOARD_ITEM* nearestEdge = nullptr;
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VECTOR2I itemPos = aItem->GetCenter();
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VECTOR2I nearestEdgePt = aBoardOutline.Outline( 0 ).NearestPoint( itemPos, false );
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for( int outlineIdx = 1; outlineIdx < aBoardOutline.OutlineCount(); ++outlineIdx )
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{
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VECTOR2I otherEdgePt = aBoardOutline.Outline( outlineIdx ).NearestPoint( itemPos, false );
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if( otherEdgePt.SquaredDistance( itemPos ) < nearestEdgePt.SquaredDistance( itemPos ) )
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nearestEdgePt = otherEdgePt;
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}
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for( BOARD_ITEM* edge : m_edgesTree.GetObjectsAt( nearestEdgePt, Edge_Cuts, m_epsilon ) )
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{
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if( edge->HitTest( nearestEdgePt, m_epsilon ) )
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{
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nearestEdge = edge;
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break;
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}
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}
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if( !nearestEdge )
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return;
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auto constraint = m_drcEngine->EvalRules( SILK_CLEARANCE_CONSTRAINT, nearestEdge, aItem, UNDEFINED_LAYER );
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int minClearance = constraint.GetValue().Min();
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SILK_EDGE_CLEARANCE );
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// Report clearance info if there is any, even though crossing is just a straight-up collision
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if( minClearance > 0 )
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{
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drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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minClearance,
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0 ) );
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}
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drcItem->SetItems( nearestEdge->m_Uuid, aItem->m_Uuid );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportTwoPointGeometry( drcItem, nearestEdgePt, nearestEdgePt, nearestEdgePt, aItem->GetLayer() );
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}
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}
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#if 0
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// If you want "Silk outside board edge" errors:
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else if( disposition == OFF_BOARD )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SILK_EDGE_CLEARANCE );
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drcItem->SetErrorMessage( _( "Silkscreen outside board edge" ) );
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drcItem->SetItems( aItem->m_Uuid );
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reportTwoPointGeometry( drcItem, aItem->GetCenter(), aItem->GetCenter(), aItem->GetCenter(),
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aItem->GetLayer() );
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}
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#endif
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}
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bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::testAgainstEdge( BOARD_ITEM* item, SHAPE* itemShape, BOARD_ITEM* edge,
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DRC_CONSTRAINT_T aConstraintType, PCB_DRC_CODE aErrorCode )
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{
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std::shared_ptr<SHAPE> shape;
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if( edge->Type() == PCB_PAD_T )
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shape = edge->GetEffectiveHoleShape();
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else
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shape = edge->GetEffectiveShape( Edge_Cuts );
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auto constraint = m_drcEngine->EvalRules( aConstraintType, edge, item, UNDEFINED_LAYER );
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int minClearance = constraint.GetValue().Min();
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int actual;
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VECTOR2I pos;
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && minClearance >= 0 )
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{
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if( itemShape->Collide( shape.get(), std::max( 0, minClearance - m_epsilon ), &actual, &pos ) )
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{
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if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
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{
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// Edge collisions are allowed inside the holes of castellated pads
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for( PAD* castellatedPad : m_castellatedPads )
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{
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if( castellatedPad->GetEffectiveHoleShape()->Collide( pos ) )
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return true;
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}
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}
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( aErrorCode );
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// Only report clearance info if there is any; otherwise it's just a straight collision
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if( minClearance > 0 )
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{
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drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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minClearance,
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actual ) );
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}
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drcItem->SetItems( edge->m_Uuid, item->m_Uuid );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportTwoItemGeometry( drcItem, pos, edge, item, Edge_Cuts, actual );
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if( aErrorCode == DRCE_SILK_EDGE_CLEARANCE )
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m_silkDisposition[item] = CROSSES_EDGE;
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if( item->Type() == PCB_TRACE_T || item->Type() == PCB_ARC_T )
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return m_drcEngine->GetReportAllTrackErrors();
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else
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return false; // don't report violations with multiple edges; one is enough
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}
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}
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return true;
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}
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bool DRC_TEST_PROVIDER_EDGE_CLEARANCE::Run()
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{
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_EDGE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking copper to board edge clearances..." ) ) )
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return false; // DRC cancelled
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_EDGE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking silk to board edge clearances..." ) ) )
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return false; // DRC cancelled
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}
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else
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{
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REPORT_AUX( wxT( "Edge clearance violations ignored. Tests not run." ) );
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return true; // continue with other tests
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}
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m_board = m_drcEngine->GetBoard();
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m_castellatedPads.clear();
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m_epsilon = m_board->GetDesignSettings().GetDRCEpsilon();
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m_edgesTree.clear();
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m_silkDisposition.clear();
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DRC_CONSTRAINT worstClearanceConstraint;
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if( m_drcEngine->QueryWorstConstraint( EDGE_CLEARANCE_CONSTRAINT, worstClearanceConstraint ) )
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m_largestEdgeClearance = worstClearanceConstraint.GetValue().Min();
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/*
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* Build an RTree of the various edges (including NPTH holes) and margins found on the board.
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*/
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std::vector<std::unique_ptr<PCB_SHAPE>> edges;
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forEachGeometryItem( { PCB_SHAPE_T }, LSET( { Edge_Cuts, Margin } ),
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[&]( BOARD_ITEM *item ) -> bool
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{
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PCB_SHAPE* shape = static_cast<PCB_SHAPE*>( item );
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STROKE_PARAMS stroke = shape->GetStroke();
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if( item->IsOnLayer( Edge_Cuts ) )
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stroke.SetWidth( 0 );
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if( shape->GetShape() == SHAPE_T::RECTANGLE && !shape->IsSolidFill() )
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{
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// A single rectangle for the board would defeat the RTree, so convert to edges
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if( shape->GetCornerRadius() > 0 )
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{
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for( SHAPE* subshape : shape->MakeEffectiveShapes( true ) )
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{
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if( SHAPE_SEGMENT* segment = dynamic_cast<SHAPE_SEGMENT*>( subshape ) )
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{
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStart( segment->GetStart() );
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edges.back()->SetEnd( segment->GetEnd() );
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edges.back()->SetStroke( stroke );
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}
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else if( SHAPE_ARC* arc = dynamic_cast<SHAPE_ARC*>( subshape ) )
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{
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::ARC );
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edges.back()->SetArcGeometry( arc->GetP0(), arc->GetArcMid(), arc->GetP1() );
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edges.back()->SetStroke( stroke );
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}
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else
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{
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wxFAIL_MSG(
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wxString::Format( "Unexpected effective shape type %d for rounded rectangle",
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(int) subshape->Type() ) );
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continue;
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}
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}
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}
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else
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{
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetEndX( shape->GetStartX() );
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edges.back()->SetStroke( stroke );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetEndY( shape->GetStartY() );
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edges.back()->SetStroke( stroke );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStartX( shape->GetEndX() );
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edges.back()->SetStroke( stroke );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStartY( shape->GetEndY() );
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edges.back()->SetStroke( stroke );
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}
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}
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else if( shape->GetShape() == SHAPE_T::POLY && !shape->IsSolidFill() )
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{
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// A single polygon for the board would defeat the RTree, so convert to edges.
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SHAPE_LINE_CHAIN poly = shape->GetPolyShape().Outline( 0 );
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for( size_t ii = 0; ii < poly.GetSegmentCount(); ++ii )
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{
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SEG seg = poly.CSegment( ii );
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetShape( SHAPE_T::SEGMENT );
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edges.back()->SetStart( seg.A );
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edges.back()->SetEnd( seg.B );
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edges.back()->SetStroke( stroke );
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}
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}
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else
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{
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edges.emplace_back( static_cast<PCB_SHAPE*>( shape->Clone() ) );
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edges.back()->SetStroke( stroke );
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}
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return true;
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} );
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for( const std::unique_ptr<PCB_SHAPE>& edge : edges )
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{
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for( PCB_LAYER_ID layer : { Edge_Cuts, Margin } )
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{
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if( edge->IsOnLayer( layer ) )
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m_edgesTree.Insert( edge.get(), layer, m_largestEdgeClearance );
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}
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}
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for( FOOTPRINT* footprint : m_board->Footprints() )
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{
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for( PAD* pad : footprint->Pads() )
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{
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if( pad->GetAttribute() == PAD_ATTRIB::NPTH && pad->HasHole() )
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{
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// edge-clearances are for milling tolerances (drilling tolerances are handled
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// by hole-clearances)
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if( pad->GetDrillSizeX() != pad->GetDrillSizeY() )
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m_edgesTree.Insert( pad, Edge_Cuts, m_largestEdgeClearance );
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}
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if( pad->GetProperty() == PAD_PROP::CASTELLATED )
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m_castellatedPads.push_back( pad );
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}
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}
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/*
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* Test copper and silk items against the set of edges.
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*/
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const int progressDelta = 200;
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int count = 0;
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int ii = 0;
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forEachGeometryItem( s_allBasicItems, LSET::AllLayersMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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count++;
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return true;
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} );
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forEachGeometryItem( s_allBasicItems, LSET::AllLayersMask(),
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[&]( BOARD_ITEM *item ) -> bool
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{
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bool testCopper = !m_drcEngine->IsErrorLimitExceeded( DRCE_EDGE_CLEARANCE );
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bool testSilk = !m_drcEngine->IsErrorLimitExceeded( DRCE_SILK_EDGE_CLEARANCE );
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if( !testCopper && !testSilk )
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return false; // All limits exceeded; we're done
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if( !reportProgress( ii++, count, progressDelta ) )
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return false; // DRC cancelled; we're done
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if( isInvisibleText( item ) )
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return true; // Continue with other items
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if( item->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( item );
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if( pad->GetProperty() == PAD_PROP::CASTELLATED || pad->GetAttribute() == PAD_ATTRIB::CONN )
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return true; // Continue with other items
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}
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std::vector<PCB_LAYER_ID> layersToTest;
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switch( item->Type() )
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{
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case PCB_PAD_T:
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layersToTest = static_cast<PAD*>( item )->Padstack().UniqueLayers();
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break;
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case PCB_VIA_T:
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layersToTest = static_cast<PCB_VIA*>( item )->Padstack().UniqueLayers();
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break;
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case PCB_ZONE_T:
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for( PCB_LAYER_ID layer : item->GetLayerSet() )
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layersToTest.push_back( layer );
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break;
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default:
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layersToTest = { UNDEFINED_LAYER };
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}
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for( PCB_LAYER_ID shapeLayer : layersToTest )
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{
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const std::shared_ptr<SHAPE>& itemShape = item->GetEffectiveShape( shapeLayer );
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for( PCB_LAYER_ID testLayer : { Edge_Cuts, Margin } )
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{
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if( testCopper && item->IsOnCopperLayer() )
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{
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m_edgesTree.QueryColliding( item, shapeLayer, testLayer, nullptr,
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[&]( BOARD_ITEM* edge ) -> bool
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{
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return testAgainstEdge( item, itemShape.get(), edge,
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EDGE_CLEARANCE_CONSTRAINT,
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DRCE_EDGE_CLEARANCE );
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},
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m_largestEdgeClearance );
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}
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if( testSilk && ( item->IsOnLayer( F_SilkS ) || item->IsOnLayer( B_SilkS ) ) )
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{
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m_edgesTree.QueryColliding( item, shapeLayer, testLayer, nullptr,
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[&]( BOARD_ITEM* edge ) -> bool
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{
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return testAgainstEdge( item, itemShape.get(), edge,
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SILK_CLEARANCE_CONSTRAINT,
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DRCE_SILK_EDGE_CLEARANCE );
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},
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m_largestEdgeClearance );
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}
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}
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if( testSilk && ( item->IsOnLayer( F_SilkS ) || item->IsOnLayer( B_SilkS ) ) )
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{
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if( m_silkDisposition[item] == UNKNOWN && m_board->BoardOutline()->HasOutline() )
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resolveSilkDisposition( item, itemShape.get(), m_board->BoardOutline()->GetOutline() );
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}
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}
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return true;
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} );
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return !m_drcEngine->IsCancelled();
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}
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|
|
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namespace detail
|
|
{
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static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_EDGE_CLEARANCE> dummy;
|
|
}
|