Seth Hillbrand
dc53c96d6f
Replace SEG::operator< with a lexicographic comparator for the sweep-line segment sort. The default operator delegates to VECTOR2I magnitude comparison which violates strict weak ordering required by std::sort. Also guard against null fill polygons from GetFill() when a zone is not filled on a layer.
1431 lines
55 KiB
C++
1431 lines
55 KiB
C++
/*
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* This program source code file is part of KiCad, a free EDA CAD application.
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*
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* Copyright The KiCad Developers.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, you may find one here:
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* http://www.gnu.org/licenses/old-licenses/gpl-2.0.html
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* or you may search the http://www.gnu.org website for the version 2 license,
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* or you may write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA
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*/
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#include <common.h>
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#include <board_design_settings.h>
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#include <footprint.h>
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#include <layer_range.h>
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#include <pcb_shape.h>
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#include <pad.h>
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#include <pcb_track.h>
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#include <thread_pool.h>
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#include <zone.h>
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#include <geometry/seg.h>
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#include <geometry/shape_poly_set.h>
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#include <geometry/shape_segment.h>
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#include <drc/drc_engine.h>
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#include <drc/drc_rtree.h>
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#include <drc/drc_item.h>
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#include <drc/drc_rule.h>
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#include <drc/drc_test_provider.h>
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#include <drc/drc_creepage_utils.h>
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#include <pcb_dimension.h>
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#include <future>
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/*
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Copper clearance test. Checks all copper items (pads, vias, tracks, drawings, zones) for their
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electrical clearance.
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Errors generated:
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- DRCE_CLEARANCE
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- DRCE_HOLE_CLEARANCE
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- DRCE_TRACKS_CROSSING
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- DRCE_ZONES_INTERSECT
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- DRCE_SHORTING_ITEMS
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*/
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class DRC_TEST_PROVIDER_COPPER_CLEARANCE : public DRC_TEST_PROVIDER
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{
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public:
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DRC_TEST_PROVIDER_COPPER_CLEARANCE () :
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DRC_TEST_PROVIDER(),
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m_drcEpsilon( 0 )
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{}
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virtual ~DRC_TEST_PROVIDER_COPPER_CLEARANCE() = default;
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virtual bool Run() override;
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virtual const wxString GetName() const override { return wxT( "clearance" ); };
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private:
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/**
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* Checks for track/via/hole <-> clearance
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* @param item Track to text
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* @param itemShape Primitive track shape
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* @param layer Which layer to test (in case of vias this can be multiple
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* @param other item against which to test the track item
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* @return false if there is a clearance violation reported, true if there is none
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*/
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bool testSingleLayerItemAgainstItem( BOARD_ITEM* item, SHAPE* itemShape, PCB_LAYER_ID layer,
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BOARD_ITEM* other );
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void testTrackClearances();
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bool testPadAgainstItem( PAD* pad, SHAPE* padShape, PCB_LAYER_ID layer, BOARD_ITEM* other );
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void testPadClearances();
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void testGraphicClearances();
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void testZonesToZones();
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void testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone, PCB_LAYER_ID aLayer );
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void testKnockoutTextAgainstZone( BOARD_ITEM* aText, NETINFO_ITEM** aInheritedNet, ZONE* aZone );
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private:
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int m_drcEpsilon;
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};
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::Run()
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{
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m_board = m_drcEngine->GetBoard();
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if( m_board->m_DRCMaxClearance <= 0 )
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{
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REPORT_AUX( wxT( "No Clearance constraints found. Tests not run." ) );
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return true; // continue with other tests
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}
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m_drcEpsilon = m_board->GetDesignSettings().GetDRCEpsilon();
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking track & via clearances..." ) ) )
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return false; // DRC cancelled
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testTrackClearances();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking hole clearances..." ) ) )
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return false; // DRC cancelled
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testTrackClearances();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking pad clearances..." ) ) )
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return false; // DRC cancelled
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testPadClearances();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS )
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|| !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking pads..." ) ) )
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return false; // DRC cancelled
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testPadClearances();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking copper graphic clearances..." ) ) )
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return false; // DRC cancelled
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testGraphicClearances();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking copper graphic hole clearances..." ) ) )
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return false; // DRC cancelled
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testGraphicClearances();
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}
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if( !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ) )
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{
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if( !reportPhase( _( "Checking copper zone clearances..." ) ) )
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return false; // DRC cancelled
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testZonesToZones();
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}
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else if( !m_drcEngine->IsErrorLimitExceeded( DRCE_ZONES_INTERSECT ) )
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{
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if( !reportPhase( _( "Checking zones..." ) ) )
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return false; // DRC cancelled
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testZonesToZones();
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}
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return !m_drcEngine->IsCancelled();
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}
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bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testSingleLayerItemAgainstItem( BOARD_ITEM* item,
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SHAPE* itemShape,
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PCB_LAYER_ID layer,
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BOARD_ITEM* other )
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{
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bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
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bool testShorting = !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS );
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bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
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DRC_CONSTRAINT constraint;
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int clearance = -1;
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int actual;
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VECTOR2I pos;
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bool has_error = false;
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NETINFO_ITEM* itemNet = nullptr;
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NETINFO_ITEM* otherNet = nullptr;
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if( BOARD_CONNECTED_ITEM* connectedItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( item ) )
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itemNet = connectedItem->GetNet();
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if( BOARD_CONNECTED_ITEM* connectedItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( other ) )
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otherNet = connectedItem->GetNet();
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if( itemNet == otherNet )
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testClearance = testShorting = false;
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std::shared_ptr<SHAPE> otherShape_shared_ptr;
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if( other->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( other );
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if( !pad->FlashLayer( layer ) )
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{
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if( pad->GetAttribute() == PAD_ATTRIB::NPTH )
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testClearance = testShorting = false;
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otherShape_shared_ptr = pad->GetEffectiveHoleShape();
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}
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}
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else if( other->Type() == PCB_VIA_T )
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{
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PCB_VIA* via = static_cast<PCB_VIA*>( other );
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if( !via->FlashLayer( layer ) )
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otherShape_shared_ptr = via->GetEffectiveHoleShape();
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}
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if( !otherShape_shared_ptr )
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otherShape_shared_ptr = other->GetEffectiveShape( layer );
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SHAPE* otherShape = otherShape_shared_ptr.get();
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// Collide (and generate violations) based on a well-defined order so that exclusion checking
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// against previously-generated violations will work.
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if( item->m_Uuid > other->m_Uuid )
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{
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std::swap( item, other );
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std::swap( itemShape, otherShape );
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std::swap( itemNet, otherNet );
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}
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if( testClearance || testShorting )
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{
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constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, item, other, layer );
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clearance = constraint.GetValue().Min();
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}
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
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{
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// Special processing for track:track intersections
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if( item->Type() == PCB_TRACE_T && other->Type() == PCB_TRACE_T )
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{
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PCB_TRACK* track = static_cast<PCB_TRACK*>( item );
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PCB_TRACK* otherTrack = static_cast<PCB_TRACK*>( other );
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SEG trackSeg( track->GetStart(), track->GetEnd() );
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SEG otherSeg( otherTrack->GetStart(), otherTrack->GetEnd() );
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if( OPT_VECTOR2I intersection = trackSeg.Intersect( otherSeg ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_TRACKS_CROSSING );
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drcItem->SetItems( item, other );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportTwoPointGeometry( drcItem, *intersection, *intersection, *intersection, layer );
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return false;
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}
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}
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if( itemShape->Collide( otherShape, clearance - m_drcEpsilon, &actual, &pos ) )
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{
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if( itemNet && m_drcEngine->IsNetTieExclusion( itemNet->GetNetCode(), layer, pos, other ) )
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{
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// Collision occurred as track was entering a pad marked as a net-tie. We
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// allow these.
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}
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else if( actual == 0 && otherNet && testShorting )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
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drcItem->SetErrorDetail( wxString::Format( _( "(nets %s and %s)" ),
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itemNet ? itemNet->GetNetname() : _( "<no net>" ),
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otherNet ? otherNet->GetNetname() : _( "<no net>" ) ) );
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drcItem->SetItems( item, other );
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reportTwoPointGeometry( drcItem, pos, pos, pos, layer );
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has_error = true;
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if( !m_drcEngine->GetReportAllTrackErrors() )
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return false;
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}
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else if( testClearance )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
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drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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clearance,
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actual ) );
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drcItem->SetItems( item, other );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportTwoShapeGeometry( drcItem, pos, itemShape, otherShape, layer, actual );
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has_error = true;
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if( !m_drcEngine->GetReportAllTrackErrors() )
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return false;
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}
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}
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}
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if( testHoles && ( item->HasHole() || other->HasHole() ) )
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{
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std::array<BOARD_ITEM*, 2> a{ item, other };
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std::array<BOARD_ITEM*, 2> b{ other, item };
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std::array<NETINFO_ITEM*, 2> b_net{ otherNet, itemNet };
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std::array<SHAPE*, 2> a_shape{ itemShape, otherShape };
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for( size_t ii = 0; ii < 2; ++ii )
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{
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std::shared_ptr<SHAPE_SEGMENT> holeShape;
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if( b[ii]->Type() == PCB_VIA_T )
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{
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if( b[ii]->GetLayerSet().Contains( layer ) )
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holeShape = b[ii]->GetEffectiveHoleShape();
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else
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continue;
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}
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else
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{
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if( b[ii]->HasHole() )
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holeShape = b[ii]->GetEffectiveHoleShape();
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else
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continue;
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}
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int netcode = b_net[ii] ? b_net[ii]->GetNetCode() : 0;
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if( netcode && m_drcEngine->IsNetTieExclusion( netcode, layer, holeShape->Centre(), a[ii] ) )
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continue;
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constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, b[ii], a[ii], layer );
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clearance = constraint.GetValue().Min();
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// Test for hole to item clearance even if clearance is 0, because the item cannot be
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// inside (or intersect) the hole.
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE )
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{
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if( a_shape[ii]->Collide( holeShape.get(), std::max( 0, clearance - m_drcEpsilon ),
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&actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
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drcItem->SetErrorDetail( formatMsg( clearance ? _( "(%s clearance %s; actual %s)" )
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: _( "(%s clearance %s; actual < 0)" ),
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constraint.GetName(),
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clearance,
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actual ) );
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drcItem->SetItems( a[ii], b[ii] );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportTwoShapeGeometry( drcItem, pos, a_shape[ii], holeShape.get(), layer, actual );
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return false;
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}
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}
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}
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}
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return !has_error;
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}
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void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testItemAgainstZone( BOARD_ITEM* aItem, ZONE* aZone,
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PCB_LAYER_ID aLayer )
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{
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if( !aZone->GetLayerSet().test( aLayer ) )
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return;
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if( aZone->GetNetCode() && aItem->IsConnected() )
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{
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if( aZone->GetNetCode() == static_cast<BOARD_CONNECTED_ITEM*>( aItem )->GetNetCode() )
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return;
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}
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BOX2I itemBBox = aItem->GetBoundingBox();
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BOX2I worstCaseBBox = itemBBox;
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worstCaseBBox.Inflate( m_board->m_DRCMaxClearance );
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if( !worstCaseBBox.Intersects( aZone->GetBoundingBox() ) )
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return;
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FOOTPRINT* parentFP = aItem->GetParentFootprint();
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// Ignore graphic items which implement a net-tie to the zone's net on the layer being tested.
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if( parentFP && parentFP->IsNetTie() && dynamic_cast<PCB_SHAPE*>( aItem ) )
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{
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std::set<PAD*> allowedNetTiePads;
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for( PAD* pad : parentFP->Pads() )
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{
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if( pad->GetNetCode() == aZone->GetNetCode() && aZone->GetNetCode() != 0 )
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{
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if( pad->IsOnLayer( aLayer ) )
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allowedNetTiePads.insert( pad );
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for( PAD* other : parentFP->GetNetTiePads( pad ) )
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{
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if( other->IsOnLayer( aLayer ) )
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allowedNetTiePads.insert( other );
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}
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}
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}
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if( !allowedNetTiePads.empty() )
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{
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std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape();
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for( PAD* pad : allowedNetTiePads )
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{
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if( pad->GetBoundingBox().Intersects( itemBBox )
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&& pad->GetEffectiveShape( aLayer )->Collide( itemShape.get() ) )
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{
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return;
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}
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}
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}
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}
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bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
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bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
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if( !testClearance && !testHoles )
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return;
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DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ aZone ].get();
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if( !zoneTree )
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return;
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DRC_CONSTRAINT constraint;
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int clearance = -1;
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int actual;
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VECTOR2I pos;
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if( aItem->Type() == PCB_PAD_T )
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{
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PAD* pad = static_cast<PAD*>( aItem );
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bool flashedPad = pad->FlashLayer( aLayer );
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bool platedHole = pad->HasHole() && pad->GetAttribute() == PAD_ATTRIB::PTH;
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if( !flashedPad && !platedHole )
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testClearance = false;
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}
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if( testClearance )
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{
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constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aItem, aZone, aLayer );
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clearance = constraint.GetValue().Min();
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}
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if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
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{
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std::shared_ptr<SHAPE> itemShape = aItem->GetEffectiveShape( aLayer, FLASHING::DEFAULT );
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if( zoneTree->QueryColliding( itemBBox, itemShape.get(), aLayer,
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std::max( 0, clearance - m_drcEpsilon ), &actual, &pos ) )
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{
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std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
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drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
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constraint.GetName(),
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clearance,
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actual ) );
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drcItem->SetItems( aItem, aZone );
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drcItem->SetViolatingRule( constraint.GetParentRule() );
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reportTwoItemGeometry( drcItem, pos, aItem, aZone, aLayer, actual );
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}
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}
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if( testHoles && aItem->HasHole() )
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{
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std::shared_ptr<SHAPE_SEGMENT> holeShape;
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if( aItem->Type() == PCB_VIA_T )
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{
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if( aItem->GetLayerSet().Contains( aLayer ) )
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holeShape = aItem->GetEffectiveHoleShape();
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}
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else
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{
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holeShape = aItem->GetEffectiveHoleShape();
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}
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if( holeShape )
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{
|
|
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, aItem, aZone, aLayer );
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
|
|
{
|
|
if( zoneTree->QueryColliding( itemBBox, holeShape.get(), aLayer,
|
|
std::max( 0, clearance - m_drcEpsilon ),
|
|
&actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
|
|
drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual ) );
|
|
drcItem->SetItems( aItem, aZone );
|
|
drcItem->SetViolatingRule( constraint.GetParentRule() );
|
|
|
|
std::shared_ptr<SHAPE> zoneShape = aZone->GetEffectiveShape( aLayer );
|
|
reportTwoShapeGeometry( drcItem, pos, holeShape.get(), zoneShape.get(), aLayer, actual );
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
* We have to special-case knockout text as it's most often knocked-out of a zone, so it's
|
|
* presumed to collide with one. However, if it collides with more than one, and they have
|
|
* different nets, then we have a short.
|
|
*/
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testKnockoutTextAgainstZone( BOARD_ITEM* aText,
|
|
NETINFO_ITEM** aInheritedNet,
|
|
ZONE* aZone )
|
|
{
|
|
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
|
|
bool testShorts = !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS );
|
|
|
|
if( !testClearance && !testShorts )
|
|
return;
|
|
|
|
PCB_LAYER_ID layer = aText->GetLayer();
|
|
|
|
if( !aZone->GetLayerSet().test( layer ) )
|
|
return;
|
|
|
|
BOX2I itemBBox = aText->GetBoundingBox();
|
|
BOX2I worstCaseBBox = itemBBox;
|
|
|
|
worstCaseBBox.Inflate( m_board->m_DRCMaxClearance );
|
|
|
|
if( !worstCaseBBox.Intersects( aZone->GetBoundingBox() ) )
|
|
return;
|
|
|
|
DRC_RTREE* zoneTree = m_board->m_CopperZoneRTreeCache[ aZone ].get();
|
|
|
|
if( !zoneTree )
|
|
return;
|
|
|
|
std::shared_ptr<SHAPE> itemShape = aText->GetEffectiveShape( layer, FLASHING::DEFAULT );
|
|
|
|
if( *aInheritedNet == nullptr )
|
|
{
|
|
if( zoneTree->QueryColliding( itemBBox, itemShape.get(), layer ) )
|
|
*aInheritedNet = aZone->GetNet();
|
|
}
|
|
|
|
if( *aInheritedNet == aZone->GetNet() )
|
|
return;
|
|
|
|
DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, aText, aZone, layer );
|
|
int clearance = constraint.GetValue().Min();
|
|
int actual;
|
|
VECTOR2I pos;
|
|
|
|
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance >= 0 )
|
|
{
|
|
if( zoneTree->QueryColliding( itemBBox, itemShape.get(), layer,
|
|
std::max( 0, clearance - m_drcEpsilon ), &actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drcItem;
|
|
|
|
if( testShorts && actual == 0 && *aInheritedNet )
|
|
{
|
|
drcItem = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
|
|
drcItem->SetErrorDetail( wxString::Format( _( "(nets %s and %s)" ),
|
|
( *aInheritedNet )->GetNetname(),
|
|
aZone->GetNetname() ) );
|
|
}
|
|
else
|
|
{
|
|
drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual ) );
|
|
}
|
|
|
|
drcItem->SetItems( aText, aZone );
|
|
drcItem->SetViolatingRule( constraint.GetParentRule() );
|
|
reportTwoItemGeometry( drcItem, pos, aText, aZone, layer, actual );
|
|
}
|
|
}
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testTrackClearances()
|
|
{
|
|
std::map<BOARD_ITEM*, int> freePadsUsageMap;
|
|
std::unordered_map<PTR_PTR_CACHE_KEY, LAYERS_CHECKED> checkedPairs;
|
|
std::mutex checkedPairsMutex;
|
|
std::mutex freePadsUsageMapMutex;
|
|
std::atomic<size_t> done( 0 );
|
|
size_t count = m_board->Tracks().size();
|
|
|
|
REPORT_AUX( wxString::Format( wxT( "Testing %d tracks & vias..." ), count ) );
|
|
|
|
LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() );
|
|
|
|
auto testTrack =
|
|
[&]( const int trackIdx )
|
|
{
|
|
PCB_TRACK* track = m_board->Tracks()[trackIdx];
|
|
|
|
for( PCB_LAYER_ID layer : LSET( track->GetLayerSet() & boardCopperLayers ) )
|
|
{
|
|
std::shared_ptr<SHAPE> trackShape = track->GetEffectiveShape( layer );
|
|
|
|
m_board->m_CopperItemRTreeCache->QueryColliding( track, layer, layer,
|
|
// Filter:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
BOARD_CONNECTED_ITEM* otherCItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( other );
|
|
|
|
if( otherCItem && otherCItem->GetNetCode() == track->GetNetCode() )
|
|
return false;
|
|
|
|
BOARD_ITEM* a = track;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both directions
|
|
// (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
std::lock_guard<std::mutex> lock( checkedPairsMutex );
|
|
auto it = checkedPairs.find( { a, b } );
|
|
|
|
if( it != checkedPairs.end()
|
|
&& ( it->second.layers.test( layer ) || ( it->second.has_error ) ) )
|
|
{
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
checkedPairs[ { a, b } ].layers.set( layer );
|
|
return true;
|
|
}
|
|
},
|
|
// Visitor:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
if( m_drcEngine->IsCancelled() )
|
|
return false;
|
|
|
|
if( other->Type() == PCB_PAD_T && static_cast<PAD*>( other )->IsFreePad() )
|
|
{
|
|
if( other->GetEffectiveShape( layer )->Collide( trackShape.get() ) )
|
|
{
|
|
std::lock_guard<std::mutex> lock( freePadsUsageMapMutex );
|
|
auto it = freePadsUsageMap.find( other );
|
|
|
|
if( it == freePadsUsageMap.end() )
|
|
{
|
|
freePadsUsageMap[ other ] = track->GetNetCode();
|
|
return true; // Continue colliding tests
|
|
}
|
|
else if( it->second == track->GetNetCode() )
|
|
{
|
|
return true; // Continue colliding tests
|
|
}
|
|
}
|
|
}
|
|
|
|
// If we get an error, mark the pair as having a clearance error already
|
|
if( !testSingleLayerItemAgainstItem( track, trackShape.get(), layer, other ) )
|
|
{
|
|
if( !m_drcEngine->GetReportAllTrackErrors() )
|
|
{
|
|
BOARD_ITEM* a = track;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both directions
|
|
// (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
std::lock_guard<std::mutex> lock( checkedPairsMutex );
|
|
auto it = checkedPairs.find( { a, b } );
|
|
|
|
if( it != checkedPairs.end() )
|
|
it->second.has_error = true;
|
|
|
|
return false; // We're done with this track
|
|
}
|
|
}
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
},
|
|
m_board->m_DRCMaxClearance );
|
|
|
|
for( ZONE* zone : m_board->m_DRCCopperZones )
|
|
{
|
|
testItemAgainstZone( track, zone, layer );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
break;
|
|
}
|
|
}
|
|
|
|
done.fetch_add( 1 );
|
|
};
|
|
|
|
thread_pool& tp = GetKiCadThreadPool();
|
|
|
|
auto track_futures = tp.submit_loop( 0, m_board->Tracks().size(), testTrack );
|
|
|
|
while( done < count )
|
|
{
|
|
reportProgress( done, count );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
{
|
|
// Wait for the submitted loop tasks to finish
|
|
track_futures.wait();
|
|
break;
|
|
}
|
|
|
|
std::this_thread::sleep_for( std::chrono::milliseconds( 250 ) );
|
|
}
|
|
}
|
|
|
|
|
|
bool DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadAgainstItem( PAD* pad, SHAPE* padShape,
|
|
PCB_LAYER_ID aLayer,
|
|
BOARD_ITEM* other )
|
|
{
|
|
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
|
|
bool testShorting = !m_drcEngine->IsErrorLimitExceeded( DRCE_SHORTING_ITEMS );
|
|
bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE );
|
|
|
|
// Disable some tests for net-tie objects in a footprint
|
|
if( other->GetParent() == pad->GetParent() )
|
|
{
|
|
FOOTPRINT* fp = pad->GetParentFootprint();
|
|
std::map<wxString, int> padToNetTieGroupMap = fp->MapPadNumbersToNetTieGroups();
|
|
int padGroupIdx = padToNetTieGroupMap[ pad->GetNumber() ];
|
|
|
|
if( other->Type() == PCB_PAD_T )
|
|
{
|
|
PAD* otherPad = static_cast<PAD*>( other );
|
|
|
|
if( padGroupIdx >= 0 && padGroupIdx == padToNetTieGroupMap[ otherPad->GetNumber() ] )
|
|
testClearance = testShorting = false;
|
|
|
|
if( pad->SameLogicalPadAs( otherPad ) )
|
|
testHoles = false;
|
|
}
|
|
|
|
if( other->Type() == PCB_SHAPE_T && padGroupIdx >= 0 )
|
|
testClearance = testShorting = false;
|
|
}
|
|
|
|
BOARD_CONNECTED_ITEM* otherCItem = dynamic_cast<BOARD_CONNECTED_ITEM*>( other );
|
|
PAD* otherPad = nullptr;
|
|
PCB_VIA* otherVia = nullptr;
|
|
|
|
if( other->Type() == PCB_PAD_T )
|
|
otherPad = static_cast<PAD*>( other );
|
|
|
|
if( other->Type() == PCB_VIA_T )
|
|
otherVia = static_cast<PCB_VIA*>( other );
|
|
|
|
if( !IsCopperLayer( aLayer ) )
|
|
testClearance = testShorting = false;
|
|
|
|
// A NPTH has no cylinder, but it may still have pads on some layers
|
|
if( pad->GetAttribute() == PAD_ATTRIB::NPTH && !pad->FlashLayer( aLayer ) )
|
|
testClearance = testShorting = false;
|
|
|
|
if( otherPad && otherPad->GetAttribute() == PAD_ATTRIB::NPTH && !otherPad->FlashLayer( aLayer ) )
|
|
testClearance = testShorting = false;
|
|
|
|
// Track clearances are tested in testTrackClearances()
|
|
if( dynamic_cast<PCB_TRACK*>( other) )
|
|
testClearance = testShorting = false;
|
|
|
|
// Graphic clearances are tested in testGraphicClearances()
|
|
if( dynamic_cast<PCB_SHAPE*>( other ) )
|
|
testClearance = testShorting = false;
|
|
|
|
int padNet = pad->GetNetCode();
|
|
int otherNet = otherCItem ? otherCItem->GetNetCode() : 0;
|
|
|
|
// Other objects of the same (defined) net get a waiver on clearance and hole tests
|
|
if( otherNet && otherNet == padNet )
|
|
{
|
|
testClearance = testShorting = false;
|
|
testHoles = false;
|
|
}
|
|
|
|
if( !( pad->GetDrillSize().x > 0 )
|
|
&& !( otherPad && otherPad->GetDrillSize().x > 0 )
|
|
&& !( otherVia && otherVia->GetDrill() > 0 ) )
|
|
{
|
|
testHoles = false;
|
|
}
|
|
|
|
if( !testClearance && !testShorting && !testHoles )
|
|
return true;
|
|
|
|
std::shared_ptr<SHAPE> otherShape = other->GetEffectiveShape( aLayer );
|
|
DRC_CONSTRAINT constraint;
|
|
int clearance = 0;
|
|
int actual = 0;
|
|
VECTOR2I pos;
|
|
bool has_error = false;
|
|
|
|
auto sub_e = [this]( int aclearance )
|
|
{
|
|
return std::max( 0, aclearance - m_drcEpsilon );
|
|
};
|
|
|
|
if( otherPad && pad->SameLogicalPadAs( otherPad ) )
|
|
{
|
|
// If pads are equivalent (ie: from the same footprint with the same pad number)...
|
|
// ... and have "real" nets...
|
|
// then they must be the same net
|
|
if( testShorting )
|
|
{
|
|
if( pad->GetNetCode() == 0 || pad->GetNetCode() == otherPad->GetNetCode() )
|
|
return true;
|
|
|
|
if( pad->GetShortNetname().StartsWith( wxS( "unconnected-(" ) )
|
|
&& otherPad->GetShortNetname().StartsWith( wxS( "unconnected-(" ) ) )
|
|
{
|
|
return true;
|
|
}
|
|
|
|
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
|
|
drcItem->SetErrorDetail( wxString::Format( _( "(nets %s and %s)" ),
|
|
pad->GetNetname(),
|
|
otherPad->GetNetname() ) );
|
|
drcItem->SetItems( pad, otherPad );
|
|
reportViolation( drcItem, otherPad->GetPosition(), aLayer );
|
|
has_error = true;
|
|
}
|
|
|
|
return !has_error;
|
|
}
|
|
|
|
if( testClearance || testShorting )
|
|
{
|
|
constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, pad, other, aLayer );
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
|
|
{
|
|
if( padShape->Collide( otherShape.get(), sub_e( clearance ), &actual, &pos ) )
|
|
{
|
|
if( m_drcEngine->IsNetTieExclusion( pad->GetNetCode(), aLayer, pos, other ) )
|
|
{
|
|
// Pads connected to pads of a net-tie footprint are allowed to collide
|
|
// with the net-tie footprint's graphics.
|
|
}
|
|
else if( actual == 0 && padNet && otherNet && testShorting )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_SHORTING_ITEMS );
|
|
drcItem->SetErrorDetail( wxString::Format( _( "(nets %s and %s)" ),
|
|
pad->GetNetname(),
|
|
otherCItem->GetNetname() ) );
|
|
drcItem->SetItems( pad, other );
|
|
reportTwoPointGeometry( drcItem, pos, pos, pos, aLayer );
|
|
has_error = true;
|
|
testHoles = false; // No need for multiple violations
|
|
}
|
|
else if( testClearance )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
clearance,
|
|
actual ) );
|
|
drcItem->SetItems( pad, other );
|
|
drcItem->SetViolatingRule( constraint.GetParentRule() );
|
|
reportTwoItemGeometry( drcItem, pos, pad, other, aLayer, actual );
|
|
has_error = true;
|
|
testHoles = false; // No need for multiple violations
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
auto doTestHole =
|
|
[&]( BOARD_ITEM* item, SHAPE* shape, BOARD_ITEM* otherItem, SHAPE* aOtherShape, int aClearance )
|
|
{
|
|
if( shape->Collide( aOtherShape, sub_e( aClearance ), &actual, &pos ) )
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drcItem = DRC_ITEM::Create( DRCE_HOLE_CLEARANCE );
|
|
drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
aClearance,
|
|
actual ) );
|
|
drcItem->SetItems( item, otherItem );
|
|
drcItem->SetViolatingRule( constraint.GetParentRule() );
|
|
reportTwoShapeGeometry( drcItem, pos, shape, aOtherShape, aLayer, actual );
|
|
has_error = true;
|
|
testHoles = false; // No need for multiple violations
|
|
}
|
|
};
|
|
|
|
if( testHoles )
|
|
{
|
|
constraint = m_drcEngine->EvalRules( HOLE_CLEARANCE_CONSTRAINT, pad, other, aLayer );
|
|
|
|
if( constraint.GetSeverity() == RPT_SEVERITY_IGNORE )
|
|
testHoles = false;
|
|
}
|
|
|
|
if( testHoles && otherPad && otherPad->HasHole() )
|
|
{
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
if( !pad->FlashLayer( aLayer ) )
|
|
clearance = 0;
|
|
|
|
if( clearance > 0 )
|
|
doTestHole( pad, padShape, otherPad, otherPad->GetEffectiveHoleShape().get(), clearance );
|
|
}
|
|
|
|
if( testHoles && otherVia && otherVia->HasHole() )
|
|
{
|
|
clearance = constraint.GetValue().Min();
|
|
|
|
if( !otherVia->IsOnLayer( aLayer ) )
|
|
clearance = 0;
|
|
|
|
if( clearance > 0 )
|
|
doTestHole( pad, padShape, otherVia, otherVia->GetEffectiveHoleShape().get(), clearance );
|
|
}
|
|
|
|
return !has_error;
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testPadClearances( )
|
|
{
|
|
thread_pool& tp = GetKiCadThreadPool();
|
|
std::atomic<size_t> done( 1 );
|
|
|
|
std::unordered_map<PTR_PTR_CACHE_KEY, LAYERS_CHECKED> checkedPairs;
|
|
std::mutex checkedPairsMutex;
|
|
|
|
LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() );
|
|
|
|
const auto fp_check =
|
|
[&]( size_t ii )
|
|
{
|
|
FOOTPRINT* footprint = m_board->Footprints()[ ii ];
|
|
|
|
for( PAD* pad : footprint->Pads() )
|
|
{
|
|
for( PCB_LAYER_ID layer : LSET( pad->GetLayerSet() & boardCopperLayers ) )
|
|
{
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
|
|
std::shared_ptr<SHAPE> padShape = pad->GetEffectiveShape( layer );
|
|
|
|
m_board->m_CopperItemRTreeCache->QueryColliding( pad, layer, layer,
|
|
// Filter:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
BOARD_ITEM* a = pad;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both
|
|
// directions (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
std::lock_guard<std::mutex> lock( checkedPairsMutex );
|
|
auto it = checkedPairs.find( { a, b } );
|
|
|
|
if( it != checkedPairs.end()
|
|
&& ( it->second.layers.test( layer ) || it->second.has_error ) )
|
|
{
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
checkedPairs[ { a, b } ].layers.set( layer );
|
|
return true;
|
|
}
|
|
},
|
|
// Visitor
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
if( !testPadAgainstItem( pad, padShape.get(), layer, other ) )
|
|
{
|
|
BOARD_ITEM* a = pad;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both
|
|
// directions (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
std::lock_guard<std::mutex> lock( checkedPairsMutex );
|
|
auto it = checkedPairs.find( { a, b } );
|
|
|
|
if( it != checkedPairs.end() )
|
|
it->second.has_error = true;
|
|
}
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
},
|
|
m_board->m_DRCMaxClearance );
|
|
|
|
for( ZONE* zone : m_board->m_DRCCopperZones )
|
|
{
|
|
testItemAgainstZone( pad, zone, layer );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
|
|
done.fetch_add( 1 );
|
|
};
|
|
|
|
size_t numFootprints = m_board->Footprints().size();
|
|
auto returns = tp.submit_loop( 0, numFootprints, fp_check );
|
|
|
|
// Wait for all threads to finish
|
|
for( size_t ii = 0; ii < returns.size(); ++ii )
|
|
{
|
|
while( returns[ii].wait_for( std::chrono::milliseconds( 250 ) ) != std::future_status::ready )
|
|
reportProgress( done, numFootprints );
|
|
}
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testGraphicClearances()
|
|
{
|
|
thread_pool& tp = GetKiCadThreadPool();
|
|
size_t count = m_board->Drawings().size();
|
|
std::atomic<size_t> done( 1 );
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
count += footprint->GraphicalItems().size();
|
|
|
|
REPORT_AUX( wxString::Format( wxT( "Testing %d graphics..." ), count ) );
|
|
|
|
auto isKnockoutText =
|
|
[]( BOARD_ITEM* item )
|
|
{
|
|
return item->Type() == PCB_TEXT_T && static_cast<PCB_TEXT*>( item )->IsKnockout();
|
|
};
|
|
|
|
auto testGraphicAgainstZone =
|
|
[this, isKnockoutText]( BOARD_ITEM* item )
|
|
{
|
|
if( item->Type() == PCB_REFERENCE_IMAGE_T )
|
|
return;
|
|
|
|
if( !IsCopperLayer( item->GetLayer() ) )
|
|
return;
|
|
|
|
// Knockout text is most often knocked-out of a zone, so it's presumed to
|
|
// collide with one. However, if it collides with more than one, and they
|
|
// have different nets, then we have a short.
|
|
NETINFO_ITEM* inheritedNet = nullptr;
|
|
|
|
for( ZONE* zone : m_board->m_DRCCopperZones )
|
|
{
|
|
if( isKnockoutText( item ) )
|
|
testKnockoutTextAgainstZone( item, &inheritedNet, zone );
|
|
else
|
|
testItemAgainstZone( item, zone, item->GetLayer() );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
return;
|
|
}
|
|
};
|
|
|
|
std::unordered_map<PTR_PTR_CACHE_KEY, LAYERS_CHECKED> checkedPairs;
|
|
std::mutex checkedPairsMutex;
|
|
|
|
auto testCopperGraphic =
|
|
[this, &checkedPairs, &checkedPairsMutex]( BOARD_ITEM* graphic )
|
|
{
|
|
PCB_LAYER_ID layer = graphic->GetLayer();
|
|
|
|
m_board->m_CopperItemRTreeCache->QueryColliding( graphic, layer, layer,
|
|
// Filter:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
// Graphics are often compound shapes so ignore collisions between shapes
|
|
// in a single footprint.
|
|
if( graphic->Type() == PCB_SHAPE_T && other->Type() == PCB_SHAPE_T
|
|
&& graphic->GetParentFootprint()
|
|
&& graphic->GetParentFootprint() == other->GetParentFootprint() )
|
|
{
|
|
return false;
|
|
}
|
|
|
|
// Track clearances are tested in testTrackClearances()
|
|
if( dynamic_cast<PCB_TRACK*>( other) )
|
|
return false;
|
|
|
|
BOARD_CONNECTED_ITEM* graphic_bci = dynamic_cast<BOARD_CONNECTED_ITEM*>( graphic );
|
|
BOARD_CONNECTED_ITEM* other_bci = dynamic_cast<BOARD_CONNECTED_ITEM*>( other );
|
|
int graphicNet = graphic_bci ? graphic_bci->GetNetCode() : 0;
|
|
int otherNet = other_bci ? other_bci->GetNetCode() : 0;
|
|
|
|
if( graphicNet && graphicNet == otherNet )
|
|
return false;
|
|
|
|
BOARD_ITEM* a = graphic;
|
|
BOARD_ITEM* b = other;
|
|
|
|
// store canonical order so we don't collide in both directions
|
|
// (a:b and b:a)
|
|
if( static_cast<void*>( a ) > static_cast<void*>( b ) )
|
|
std::swap( a, b );
|
|
|
|
std::lock_guard<std::mutex> lock( checkedPairsMutex );
|
|
auto it = checkedPairs.find( { a, b } );
|
|
|
|
if( it != checkedPairs.end() && it->second.layers.test( layer ) )
|
|
{
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
checkedPairs[ { a, b } ].layers.set( layer );
|
|
return true;
|
|
}
|
|
},
|
|
// Visitor:
|
|
[&]( BOARD_ITEM* other ) -> bool
|
|
{
|
|
testSingleLayerItemAgainstItem( graphic, graphic->GetEffectiveShape().get(),
|
|
layer, other );
|
|
|
|
return !m_drcEngine->IsCancelled();
|
|
},
|
|
m_board->m_DRCMaxClearance );
|
|
};
|
|
|
|
for( BOARD_ITEM* item : m_board->Drawings() )
|
|
{
|
|
(void)tp.submit_task(
|
|
[this, item, &done, testGraphicAgainstZone, testCopperGraphic]()
|
|
{
|
|
if( !m_drcEngine->IsCancelled() )
|
|
{
|
|
testGraphicAgainstZone( item );
|
|
|
|
if( ( item->Type() == PCB_SHAPE_T || item->Type() == PCB_BARCODE_T )
|
|
&& item->IsOnCopperLayer() )
|
|
{
|
|
testCopperGraphic( static_cast<PCB_SHAPE*>( item ) );
|
|
}
|
|
|
|
done.fetch_add( 1 );
|
|
}
|
|
} );
|
|
}
|
|
|
|
for( FOOTPRINT* footprint : m_board->Footprints() )
|
|
{
|
|
(void)tp.submit_task(
|
|
[this, footprint, &done, testGraphicAgainstZone, testCopperGraphic]()
|
|
{
|
|
for( BOARD_ITEM* item : footprint->GraphicalItems() )
|
|
{
|
|
if( !m_drcEngine->IsCancelled() )
|
|
{
|
|
testGraphicAgainstZone( item );
|
|
|
|
if( ( item->Type() == PCB_SHAPE_T || item->Type() == PCB_BARCODE_T )
|
|
&& item->IsOnCopperLayer() )
|
|
{
|
|
testCopperGraphic( static_cast<PCB_SHAPE*>( item ) );
|
|
}
|
|
|
|
done.fetch_add( 1 );
|
|
}
|
|
}
|
|
} );
|
|
}
|
|
|
|
while( true )
|
|
{
|
|
reportProgress( done, count );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
break;
|
|
|
|
if( tp.wait_for( std::chrono::milliseconds( 250 ) ) )
|
|
break;
|
|
}
|
|
}
|
|
|
|
|
|
void DRC_TEST_PROVIDER_COPPER_CLEARANCE::testZonesToZones()
|
|
{
|
|
bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE );
|
|
bool testIntersects = !m_drcEngine->IsErrorLimitExceeded( DRCE_ZONES_INTERSECT );
|
|
|
|
std::vector<std::map<PCB_LAYER_ID, std::vector<SEG>>> poly_segments;
|
|
poly_segments.resize( m_board->m_DRCCopperZones.size() );
|
|
|
|
thread_pool& tp = GetKiCadThreadPool();
|
|
std::atomic<size_t> done( 0 );
|
|
size_t count = 0;
|
|
|
|
auto reportZoneZoneViolation =
|
|
[this]( ZONE* zoneA, ZONE* zoneB, VECTOR2I& pt, int actual, const DRC_CONSTRAINT& constraint,
|
|
PCB_LAYER_ID layer ) -> void
|
|
{
|
|
std::shared_ptr<DRC_ITEM> drcItem;
|
|
|
|
if( constraint.IsNull() )
|
|
{
|
|
drcItem = DRC_ITEM::Create( DRCE_ZONES_INTERSECT );
|
|
drcItem->SetErrorDetail( _( "(intersecting zones must have distinct priorities)" ) );
|
|
drcItem->SetItems( zoneA, zoneB );
|
|
reportViolation( drcItem, pt, layer );
|
|
}
|
|
else
|
|
{
|
|
drcItem = DRC_ITEM::Create( DRCE_CLEARANCE );
|
|
drcItem->SetErrorDetail( formatMsg( _( "(%s clearance %s; actual %s)" ),
|
|
constraint.GetName(),
|
|
constraint.GetValue().Min(),
|
|
std::max( actual, 0 ) ) );
|
|
drcItem->SetItems( zoneA, zoneB );
|
|
drcItem->SetViolatingRule( constraint.GetParentRule() );
|
|
reportTwoItemGeometry( drcItem, pt, zoneA, zoneB, layer, actual );
|
|
}
|
|
};
|
|
|
|
auto checkZones =
|
|
[this, testClearance, testIntersects, reportZoneZoneViolation, &poly_segments, &done]
|
|
( int zoneA_idx, int zoneB_idx, bool sameNet, PCB_LAYER_ID layer ) -> void
|
|
{
|
|
ZONE* zoneA = m_board->m_DRCCopperZones[zoneA_idx];
|
|
ZONE* zoneB = m_board->m_DRCCopperZones[zoneB_idx];
|
|
int actual = 0;
|
|
VECTOR2I pt;
|
|
|
|
if( sameNet && testIntersects )
|
|
{
|
|
if( zoneA->Outline()->Collide( zoneB->Outline(), 0, &actual, &pt ) )
|
|
{
|
|
done.fetch_add( 1 );
|
|
reportZoneZoneViolation( zoneA, zoneB, pt, actual, DRC_CONSTRAINT(), layer );
|
|
return;
|
|
}
|
|
}
|
|
else if( !sameNet && testClearance )
|
|
{
|
|
DRC_CONSTRAINT constraint = m_drcEngine->EvalRules( CLEARANCE_CONSTRAINT, zoneA, zoneB, layer );
|
|
int clearance = constraint.GetValue().Min();
|
|
|
|
if( constraint.GetSeverity() != RPT_SEVERITY_IGNORE && clearance > 0 )
|
|
{
|
|
std::map<VECTOR2I, int> conflictPoints;
|
|
|
|
std::vector<SEG>& refSegments = poly_segments[zoneA_idx][layer];
|
|
std::vector<SEG>& testSegments = poly_segments[zoneB_idx][layer];
|
|
|
|
// Iterate through all the segments in zoneA
|
|
for( SEG& refSegment : refSegments )
|
|
{
|
|
// Iterate through all the segments in zoneB
|
|
for( SEG& testSegment : testSegments )
|
|
{
|
|
// We have ensured that the 'A' segment starts before the 'B' segment, so if the
|
|
// 'A' segment ends before the 'B' segment starts, we can skip to the next 'A'
|
|
if( refSegment.B.x < testSegment.A.x )
|
|
break;
|
|
|
|
int64_t dist_sq = 0;
|
|
VECTOR2I other_pt;
|
|
refSegment.NearestPoints( testSegment, pt, other_pt, dist_sq );
|
|
actual = std::floor( std::sqrt( dist_sq ) + 0.5 );
|
|
|
|
if( actual < clearance )
|
|
{
|
|
done.fetch_add( 1 );
|
|
reportZoneZoneViolation( zoneA, zoneB, pt, actual, constraint, layer );
|
|
return;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
done.fetch_add( 1 );
|
|
};
|
|
|
|
// Pre-sort zones into layers
|
|
std::map<PCB_LAYER_ID, std::vector<size_t>> zone_idx_by_layer;
|
|
|
|
for ( size_t ii = 0; ii < m_board->m_DRCCopperZones.size(); ii++ )
|
|
{
|
|
ZONE* zone = m_board->m_DRCCopperZones[ii];
|
|
|
|
for( PCB_LAYER_ID layer : zone->GetLayerSet() )
|
|
{
|
|
if( !IsCopperLayer( layer ) )
|
|
continue;
|
|
|
|
zone_idx_by_layer[layer].push_back( ii );
|
|
}
|
|
}
|
|
|
|
for( PCB_LAYER_ID layer : LAYER_RANGE( F_Cu, B_Cu, m_board->GetCopperLayerCount() ) )
|
|
{
|
|
// Skip over layers not used on the current board
|
|
if( !m_board->IsLayerEnabled( layer ) )
|
|
continue;
|
|
|
|
for( size_t ii : zone_idx_by_layer[layer] )
|
|
{
|
|
if( SHAPE_POLY_SET* poly = m_board->m_DRCCopperZones[ii]->GetFill( layer ) )
|
|
{
|
|
std::vector<SEG>& zone_layer_poly_segs = poly_segments[ii][layer];
|
|
zone_layer_poly_segs.reserve( poly->FullPointCount() );
|
|
|
|
for( auto it = poly->IterateSegmentsWithHoles(); it; it++ )
|
|
{
|
|
SEG seg = *it;
|
|
|
|
if( seg.A.x > seg.B.x )
|
|
seg.Reverse();
|
|
|
|
zone_layer_poly_segs.push_back( seg );
|
|
}
|
|
|
|
// Sort by x-coordinates for the sweep-line optimization in the inner
|
|
// loop. SEG::operator< must not be used here because it delegates to
|
|
// VECTOR2I::operator< which compares by magnitude, violating strict
|
|
// weak ordering when mixed with VECTOR2I::operator== for tie-breaking.
|
|
std::sort( zone_layer_poly_segs.begin(), zone_layer_poly_segs.end(),
|
|
[]( const SEG& a, const SEG& b ) -> bool
|
|
{
|
|
if( a.A.x != b.A.x )
|
|
return a.A.x < b.A.x;
|
|
|
|
if( a.A.y != b.A.y )
|
|
return a.A.y < b.A.y;
|
|
|
|
if( a.B.x != b.B.x )
|
|
return a.B.x < b.B.x;
|
|
|
|
return a.B.y < b.B.y;
|
|
} );
|
|
}
|
|
}
|
|
|
|
for( auto it_a = zone_idx_by_layer[layer].begin(); it_a != zone_idx_by_layer[layer].end(); ++it_a )
|
|
{
|
|
size_t ia = *it_a;
|
|
ZONE* zoneA = m_board->m_DRCCopperZones[ia];
|
|
|
|
for( auto it_a2 = std::next( it_a ); it_a2 != zone_idx_by_layer[layer].end(); ++it_a2 )
|
|
{
|
|
size_t ia2 = *it_a2;
|
|
ZONE* zoneB = m_board->m_DRCCopperZones[ia2];
|
|
|
|
bool sameNet = zoneA->GetNetCode() == zoneB->GetNetCode() && zoneA->GetNetCode() >= 0;
|
|
|
|
if( sameNet && zoneA->GetAssignedPriority() != zoneB->GetAssignedPriority() )
|
|
continue;
|
|
|
|
// rule areas may overlap at will
|
|
if( zoneA->GetIsRuleArea() || zoneB->GetIsRuleArea() )
|
|
continue;
|
|
|
|
// Examine a candidate zone: compare zoneB to zoneA
|
|
SHAPE_POLY_SET* polyA = nullptr;
|
|
SHAPE_POLY_SET* polyB = nullptr;
|
|
|
|
if( sameNet )
|
|
{
|
|
polyA = zoneA->Outline();
|
|
polyB = zoneB->Outline();
|
|
}
|
|
else
|
|
{
|
|
polyA = zoneA->GetFill( layer );
|
|
polyB = zoneB->GetFill( layer );
|
|
}
|
|
|
|
if( !polyA || !polyB
|
|
|| !polyA->BBoxFromCaches().Intersects( polyB->BBoxFromCaches() ) )
|
|
continue;
|
|
|
|
count++;
|
|
(void)tp.submit_task(
|
|
[checkZones, ia, ia2, sameNet, layer]()
|
|
{
|
|
checkZones( ia, ia2, sameNet, layer );
|
|
} );
|
|
}
|
|
}
|
|
}
|
|
|
|
while( true )
|
|
{
|
|
reportProgress( done, count );
|
|
|
|
if( m_drcEngine->IsCancelled() )
|
|
break;
|
|
|
|
if( tp.wait_for( std::chrono::milliseconds( 250 ) ) )
|
|
break;
|
|
}
|
|
}
|
|
|
|
namespace detail
|
|
{
|
|
static DRC_REGISTER_TEST_PROVIDER<DRC_TEST_PROVIDER_COPPER_CLEARANCE> dummy;
|
|
}
|