Tuning profiles build on the previous delay tuning work to allow
the definition of track geometries per-layer for a given tuning
profile. These can be calculated from a target impedance (with
all relevant geometry taken from the board stackup), or entered
manually.
Tuning profiles can be configured to enable time-domain tuning,
and to automatically generate track geometry DRC rules for net
classes which have an assigned tuning profile.
Adds a DRC check for net classes with a tuning profile assigned
which is not itself defined.
- Adds time and delay units
- Adds time domain tuning parameters entry and storage
- Adds pad-to-die delay property
- Adds time domain parameter interface for length / delay calculations
- Adds unit tracking for numerical constants through LIBEVAL
- Will need future work to truly propagate through binary expressions
- Adds time domain tuning to meander placers
- Adds time delay display to net inspector panel
- Modifies DRC to handle time domain constraints
There are two netclass name methods, which previously were not
obvious in their uses. These have been renamed to now have:
GetName() : Used for internal or tooling (e.g. netlist export) usage
GetHumanReadableName() : Used for display to users (e.g. in infobars)
Fixing the previous unclear naming will result in fewer bugs
when users start using the multiple netclass functionality, as
the incorrect usage had started creeping in to new code. Also this
will help authors of new code select the correct name method.
Recommendation is to avoid using the year nomenclature as this
information is already encoded in the git repo. Avoids needing to
repeatly update.
Also updates AUTHORS.txt from current repo with contributor names
Also reduces line-wrapping a bit.
I don't think this fixes the linked bug, but I can't reproduce it
and this was found while reviewing the code.
Fixes https://gitlab.com/kicad/code/kicad/issues/8810
ADDED Eeschema-specific netclass settings including wire and bus
thickness, color, and line style.
Netclasses override individual wire & bus colors and line styles.
If that proves an issue we might look at something more sophisticated
with inheritance.
Fixes https://gitlab.com/kicad/code/kicad/issues/4581
Various architecture upgrades to support this.
Creating a BOARD now requires a valid PROJECT, which caused
some (mostly transparent) changes to the Python API internals.
ADDED: Project local settings file
CHANGED: Board design settings are no longer stored in PCB file
CHANGED: Net classes are no longer stored in PCB file
CHANGED: Importing board settings now reads boards, not just projects
Fixes https://gitlab.com/kicad/code/kicad/-/issues/2578
Fixes https://gitlab.com/kicad/code/kicad/-/issues/4070
JamesJCode