GetSolderMaskExpansion() on PAD, PCB_TRACK, and PCB_SHAPE called
EvalRules(SOLDER_MASK_EXPANSION_CONSTRAINT) unconditionally during
DRC, even when no custom rules existed for that constraint type.
Now check HasRulesForConstraintType() first and fall back to the
direct property lookup chain when no custom rules exist.
Also fix a bug where PCB_TRACK and PCB_SHAPE returned 0 instead of
the board default mask expansion when no local override was set.
Apply the same optimization to solder paste margin lookups. Add
per-provider DRC timing via the existing KICAD_DRC_PROFILE trace mask.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/23213
The clearance cache added in b0d0dd57ef invalidates on every
SetLayer() and SetNetCode() call. The router's rule resolver
calls SetLayer() on dummy board items for every clearance
evaluation during routing. Each call acquires an exclusive
lock and linearly scans the entire cache, but dummy items
never exist in the cache, so this is pure waste.
Skip cache invalidation for items flagged ROUTER_TRANSIENT.
The flag is already set on all dummy items in the rule
resolver.
Also replace the O(n) linear scan in InvalidateClearanceCache
with targeted O(1) hash erasure per copper layer.
This breaks the view_item.h -> inspectable.h -> property.h chain that
pulled wx/propgrid/property.h into 150-200 TUs. The lean inspectable.h
now includes only wx/any.h, wx/string.h, wx/variant.h.
Headers using DECLARE_ENUM_TO_WXANY (board_item.h, sch_item.h) retain
their property.h include since the macro requires it.
When displaying pad and track clearance outlines, GetOwnClearance()
was called repeatedly during rendering, re-evaluating DRC rules on
every paint refresh. With complex DRC rules, this caused significant
slowdown.
Add a lazy-evaluated cache in DRC_ENGINE keyed by (UUID, layer) that
stores clearance values. The cache is invalidated when DRC rules
change (in InitEngine) or properties change that could affect clearance
(net, layer, pad type)
- Update VIA::GetWidth() to raise an assertion and always return a valid albeit
most likely incorrect width.
- Fix interactive via placement tool to call the correct VIA::GetWidth() which
prevents the crash/assertion. This uses the layer of the shape where the via
is being placed.
Fixes KICAD-ZY6
(cherry picked from commit 0be18638f8)
- Allow setting backdrill (from B.Cu up) and tertiary drill (from F.Cu
down) width and target layer (backdrill is inclusive)
- Allow setting post machining options (counterbore, countersink)
- Update properties for vias and THT pads
- Add output for Excellon and Gerber drill files as separated files for
different drill depths
- Add drill map output calling out post-machined holes
- Add STEP export support
- Add 3d-viewer support
- Add 2581 support using backdrill property. Post machining called out
in comments
- Add ODB++ support using separate drill file for each depth
- Add DRC check for tracks connected to pad layers that are backdrilled
or post-machined
Fixes https://gitlab.com/kicad/code/kicad/-/issues/18836
The board connectivity algorithm creates pseudo net names for footprints
that have multiple pads with the same number using a "_N" suffix. At
some point a change was made to the zone net properties dialog that
allowed choosing a pseudo net name as the net name assigned to the zone.
This caused the netlist updater to trigger a false "zone has no pads
connected" warning because the pseudo net name is not in the schematic
net list.
The warning message was not very helpful. Added the correct zone layers
and the net name assigned to the zone to the message for improved
clarity.
Fixes https://gitlab.com/kicad/code/kicad/-/issues/22133
Skip vias are vias that are flashed on their start and end layers but
have no annular rings on the interior layers and do not connect to zones
in those layers
You can now select Annular ring type "Start and end layers only". This
will prevent annular ring flashing on intermediate layers and zones
fills will provide clearance. You can still connect tracks to
intermediate layers but preventing that will fall to the designer
Fixes https://gitlab.com/kicad/code/kicad/-/issues/21433
Also convert hatched fills to solid for solder masks.
Also give track solder masks their specified
expansion when exporting to STEP.
Also implement solder masks for shapes when
exporting to STEP.
- Adds time and delay units
- Adds time domain tuning parameters entry and storage
- Adds pad-to-die delay property
- Adds time domain parameter interface for length / delay calculations
- Adds unit tracking for numerical constants through LIBEVAL
- Will need future work to truly propagate through binary expressions
- Adds time domain tuning to meander placers
- Adds time delay display to net inspector panel
- Modifies DRC to handle time domain constraints
Jeff Young