From d4cfc0464e0bfb466db44cd61d179be8255fb516 Mon Sep 17 00:00:00 2001 From: Jeff Young Date: Wed, 9 Jul 2025 11:08:31 +0100 Subject: [PATCH] Be consistent about getting board copper layers. (cherry picked from commit d2a623719bd32eaa5a6d73ffbf408a53c3e070c9) --- pcbnew/dialogs/dialog_pad_properties.cpp | 3 +-- pcbnew/drc/drc_cache_generator.cpp | 4 ++-- .../drc_test_provider_connection_width.cpp | 2 +- .../drc_test_provider_diff_pair_coupling.cpp | 6 ++--- .../drc/drc_test_provider_matched_length.cpp | 5 ++-- .../drc_test_provider_physical_clearance.cpp | 24 +++++++++---------- .../drc/drc_test_provider_sliver_checker.cpp | 3 +-- pcbnew/exporters/export_d356.cpp | 1 + pcbnew/exporters/export_hyperlynx.cpp | 5 ++-- pcbnew/exporters/gen_drill_report_files.cpp | 4 +--- .../cadstar/cadstar_pcb_archive_loader.cpp | 2 +- .../pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp | 4 +--- pcbnew/pcb_io/odbpp/odb_entity.cpp | 7 +++--- pcbnew/pcb_plot_params.cpp | 3 +-- pcbnew/pcb_track.cpp | 2 +- pcbnew/specctra_import_export/specctra.cpp | 2 +- .../specctra_export.cpp | 14 +++++------ pcbnew/tools/pcb_selection_tool.cpp | 8 +++---- pcbnew/tracks_cleaner.cpp | 2 +- pcbnew/zone_filler.cpp | 4 ++-- 20 files changed, 47 insertions(+), 58 deletions(-) diff --git a/pcbnew/dialogs/dialog_pad_properties.cpp b/pcbnew/dialogs/dialog_pad_properties.cpp index 97b685030e..bde5aa1b65 100644 --- a/pcbnew/dialogs/dialog_pad_properties.cpp +++ b/pcbnew/dialogs/dialog_pad_properties.cpp @@ -1961,8 +1961,7 @@ bool DIALOG_PAD_PROPERTIES::transferDataToPad( PAD* aPad ) case 1: // Front, back and connected padLayerMask |= LSET::AllCuMask(); - aPad->Padstack().SetUnconnectedLayerMode( - PADSTACK::UNCONNECTED_LAYER_MODE::REMOVE_EXCEPT_START_AND_END ); + aPad->Padstack().SetUnconnectedLayerMode( PADSTACK::UNCONNECTED_LAYER_MODE::REMOVE_EXCEPT_START_AND_END ); break; case 2: diff --git a/pcbnew/drc/drc_cache_generator.cpp b/pcbnew/drc/drc_cache_generator.cpp index ac77ac091f..2a8d32fc8a 100644 --- a/pcbnew/drc/drc_cache_generator.cpp +++ b/pcbnew/drc/drc_cache_generator.cpp @@ -137,7 +137,7 @@ bool DRC_CACHE_GENERATOR::Run() PCB_DIMENSION_T }; - forEachGeometryItem( itemTypes, LSET::AllCuMask(), countItems ); + forEachGeometryItem( itemTypes, boardCopperLayers, countItems ); std::future retn = tp.submit( [&]() @@ -147,7 +147,7 @@ bool DRC_CACHE_GENERATOR::Run() if( !m_board->m_CopperItemRTreeCache ) m_board->m_CopperItemRTreeCache = std::make_shared(); - forEachGeometryItem( itemTypes, LSET::AllCuMask(), addToCopperTree ); + forEachGeometryItem( itemTypes, boardCopperLayers, addToCopperTree ); } ); std::future_status status = retn.wait_for( std::chrono::milliseconds( 250 ) ); diff --git a/pcbnew/drc/drc_test_provider_connection_width.cpp b/pcbnew/drc/drc_test_provider_connection_width.cpp index e0bfac4efb..441b8c7111 100644 --- a/pcbnew/drc/drc_test_provider_connection_width.cpp +++ b/pcbnew/drc/drc_test_provider_connection_width.cpp @@ -319,7 +319,7 @@ bool DRC_TEST_PROVIDER_CONNECTION_WIDTH::Run() return false; // DRC cancelled BOARD* board = m_drcEngine->GetBoard(); - LSET copperLayerSet = board->GetEnabledLayers() & LSET::AllCuMask(); + LSET copperLayerSet = LSET::AllCuMask( board->GetCopperLayerCount() ); LSEQ copperLayers = copperLayerSet.Seq(); int epsilon = board->GetDesignSettings().GetDRCEpsilon(); diff --git a/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp b/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp index ab23285248..07f40bf217 100644 --- a/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp +++ b/pcbnew/drc/drc_test_provider_diff_pair_coupling.cpp @@ -464,7 +464,8 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run() { m_board = m_drcEngine->GetBoard(); - int epsilon = m_board->GetDesignSettings().GetDRCEpsilon(); + int epsilon = m_board->GetDesignSettings().GetDRCEpsilon(); + LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() ); std::map dpRuleMatches; @@ -524,8 +525,7 @@ bool test::DRC_TEST_PROVIDER_DIFF_PAIR_COUPLING::Run() m_board->GetConnectivity()->GetFromToCache()->Rebuild( m_board ); - forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_ARC_T }, LSET::AllCuMask(), - evaluateDpConstraints ); + forEachGeometryItem( { PCB_TRACE_T, PCB_VIA_T, PCB_ARC_T }, boardCopperLayers, evaluateDpConstraints ); drc_dbg( 10, wxT( "dp rule matches %d\n" ), (int) dpRuleMatches.size() ); diff --git a/pcbnew/drc/drc_test_provider_matched_length.cpp b/pcbnew/drc/drc_test_provider_matched_length.cpp index 6b583a3fa6..bec466cc57 100644 --- a/pcbnew/drc/drc_test_provider_matched_length.cpp +++ b/pcbnew/drc/drc_test_provider_matched_length.cpp @@ -300,6 +300,7 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode ) return false; } + LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() ); std::map > itemSets; std::shared_ptr ftCache = m_board->GetConnectivity()->GetFromToCache(); @@ -310,14 +311,14 @@ bool DRC_TEST_PROVIDER_MATCHED_LENGTH::runInternal( bool aDelayReportMode ) size_t count = 0; size_t ii = 0; - forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, LSET::AllCuMask(), + forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, boardCopperLayers, [&]( BOARD_ITEM *item ) -> bool { count++; return true; } ); - forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, LSET::AllCuMask(), + forEachGeometryItem( { PCB_TRACE_T, PCB_ARC_T, PCB_VIA_T, PCB_PAD_T }, boardCopperLayers, [&]( BOARD_ITEM *item ) -> bool { if( !reportProgress( ii++, count, progressDelta ) ) diff --git a/pcbnew/drc/drc_test_provider_physical_clearance.cpp b/pcbnew/drc/drc_test_provider_physical_clearance.cpp index 94e27a0e03..afec9ab02d 100644 --- a/pcbnew/drc/drc_test_provider_physical_clearance.cpp +++ b/pcbnew/drc/drc_test_provider_physical_clearance.cpp @@ -92,7 +92,8 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run() m_board = m_drcEngine->GetBoard(); m_itemTree.clear(); - int errorMax = m_board->GetDesignSettings().m_MaxError; + int errorMax = m_board->GetDesignSettings().m_MaxError; + LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() ); if( m_board->m_DRCMaxPhysicalClearance <= 0 ) { @@ -154,7 +155,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run() layers |= LSET( LSET::BackBoardTechMask() ).set( B_CrtYd ); if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) ) - layers |= LSET::AllCuMask(); + layers |= boardCopperLayers; } else if( item->Type() == PCB_FOOTPRINT_T ) { @@ -261,8 +262,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run() // Generate a count for progress reporting. // - forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T }, - LSET::AllCuMask(), + forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T }, boardCopperLayers, [&]( BOARD_ITEM* item ) -> bool { ZONE* zone = dynamic_cast( item ); @@ -270,7 +270,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run() if( zone && zone->GetIsRuleArea() ) return true; // Continue with other items - count += ( item->GetLayerSet() & LSET::AllCuMask() ).count(); + count += ( item->GetLayerSet() & boardCopperLayers ).count(); return true; } ); @@ -279,8 +279,7 @@ bool DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::Run() // Run clearance checks -within- polygonal items. // - forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T }, - LSET::AllCuMask(), + forEachGeometryItem( { PCB_ZONE_T, PCB_SHAPE_T }, boardCopperLayers, [&]( BOARD_ITEM* item ) -> bool { PCB_SHAPE* shape = dynamic_cast( item ); @@ -611,10 +610,8 @@ void DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testZoneLayer( ZONE* aZone, PCB_LAYER } -int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem, - SHAPE* aItemShape, - PCB_LAYER_ID aLayer, - BOARD_ITEM* aOther ) +int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem, SHAPE* aItemShape, + PCB_LAYER_ID aLayer, BOARD_ITEM* aOther ) { bool testClearance = !m_drcEngine->IsErrorLimitExceeded( DRCE_CLEARANCE ); bool testHoles = !m_drcEngine->IsErrorLimitExceeded( DRCE_HOLE_CLEARANCE ); @@ -623,6 +620,7 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem int actual; int violations = 0; VECTOR2I pos; + LSET boardCopperLayers = LSET::AllCuMask( m_board->GetCopperLayerCount() ); std::shared_ptr otherShapeStorage = aOther->GetEffectiveShape( aLayer ); SHAPE* otherShape = otherShapeStorage.get(); @@ -677,7 +675,7 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem layers |= LSET( LSET::BackBoardTechMask() ).set( B_CrtYd ); if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) ) - layers |= LSET::AllCuMask(); + layers |= boardCopperLayers; wxCHECK_MSG( layers.Contains( aLayer ), violations, wxT( "Bug! Vias should only be checked for layers on which they exist" ) ); @@ -700,7 +698,7 @@ int DRC_TEST_PROVIDER_PHYSICAL_CLEARANCE::testItemAgainstItem( BOARD_ITEM* aItem layers |= LSET( LSET::BackBoardTechMask() ).set( B_CrtYd ); if( layers.Contains( F_Cu ) && layers.Contains( B_Cu ) ) - layers |= LSET::AllCuMask(); + layers |= boardCopperLayers; wxCHECK_MSG( layers.Contains( aLayer ), violations, wxT( "Bug! Vias should only be checked for layers on which they exist" ) ); diff --git a/pcbnew/drc/drc_test_provider_sliver_checker.cpp b/pcbnew/drc/drc_test_provider_sliver_checker.cpp index d546f8b0b1..41aeed5827 100644 --- a/pcbnew/drc/drc_test_provider_sliver_checker.cpp +++ b/pcbnew/drc/drc_test_provider_sliver_checker.cpp @@ -89,8 +89,7 @@ bool DRC_TEST_PROVIDER_SLIVER_CHECKER::Run() double angleTolerance = ADVANCED_CFG::GetCfg().m_SliverAngleTolerance; double cosangleTol = 2.0 * cos( DEG2RAD( angleTolerance ) ); - LSET copperLayerSet = m_drcEngine->GetBoard()->GetEnabledLayers() & LSET::AllCuMask(); - LSEQ copperLayers = copperLayerSet.Seq(); + LSEQ copperLayers = LSET::AllCuMask( m_drcEngine->GetBoard()->GetCopperLayerCount() ).Seq(); int layerCount = copperLayers.size(); // Report progress on board zones only. Everything else is in the noise. diff --git a/pcbnew/exporters/export_d356.cpp b/pcbnew/exporters/export_d356.cpp index 06328d4134..b7a19f1dfa 100644 --- a/pcbnew/exporters/export_d356.cpp +++ b/pcbnew/exporters/export_d356.cpp @@ -55,6 +55,7 @@ static int compute_pad_access_code( BOARD *aPcb, LSET aLayerMask ) { // Non-copper is not interesting here aLayerMask &= LSET::AllCuMask(); + if( !aLayerMask.any() ) return -1; diff --git a/pcbnew/exporters/export_hyperlynx.cpp b/pcbnew/exporters/export_hyperlynx.cpp index 4237868a54..a80754cf4d 100644 --- a/pcbnew/exporters/export_hyperlynx.cpp +++ b/pcbnew/exporters/export_hyperlynx.cpp @@ -101,8 +101,7 @@ public: bool IsEmpty() const { - LSET layerMask = LSET::AllCuMask() & m_board->GetEnabledLayers(); - LSET outLayers = m_layers & layerMask; + LSET outLayers = m_layers & LSET::AllCuMask( m_board->GetCopperLayerCount() ); return outLayers.none(); } @@ -254,7 +253,7 @@ bool HYPERLYNX_EXPORTER::generateHeaders() void HYPERLYNX_EXPORTER::writeSinglePadStack( HYPERLYNX_PAD_STACK& aStack ) { - LSET layerMask = LSET::AllCuMask() & m_board->GetEnabledLayers(); + LSET layerMask = LSET::AllCuMask( m_board->GetCopperLayerCount() ); LSET outLayers = aStack.m_layers & layerMask; if( outLayers.none() ) diff --git a/pcbnew/exporters/gen_drill_report_files.cpp b/pcbnew/exporters/gen_drill_report_files.cpp index 1586f28cba..167ac51735 100644 --- a/pcbnew/exporters/gen_drill_report_files.cpp +++ b/pcbnew/exporters/gen_drill_report_files.cpp @@ -424,11 +424,9 @@ bool GENDRILL_WRITER_BASE::GenDrillReportFile( const wxString& aFullFileName ) out.Print( 0, "Copper Layer Stackup:\n" ); out.Print( 0, separator ); - LSET cu = m_pcb->GetEnabledLayers() & LSET::AllCuMask(); - int conventional_layer_num = 1; - for( PCB_LAYER_ID layer : cu.UIOrder() ) + for( PCB_LAYER_ID layer : LSET::AllCuMask( m_pcb->GetCopperLayerCount() ).UIOrder() ) { out.Print( 0, " L%-2d: %-25s %s\n", conventional_layer_num++, diff --git a/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp b/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp index f7e995bb0d..dbdebf20a2 100644 --- a/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp +++ b/pcbnew/pcb_io/cadstar/cadstar_pcb_archive_loader.cpp @@ -1031,7 +1031,7 @@ PAD* CADSTAR_PCB_ARCHIVE_LOADER::getKiCadPad( const COMPONENT_PAD& aCadstarPad, break; case PAD_SIDE::THROUGH_HOLE: - padLayerSet = LSET::AllCuMask() | LSET( { F_Mask, B_Mask, F_Paste, B_Paste } ); + padLayerSet = LSET::AllCuMask( m_numCopperLayers ) | LSET( { F_Mask, B_Mask, F_Paste, B_Paste } ); break; default: diff --git a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp index b0a91a4dfd..f2a1a61fa0 100644 --- a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp +++ b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.cpp @@ -1377,9 +1377,7 @@ void PCB_IO_KICAD_SEXPR::formatLayers( LSET aLayerMask, bool aEnumerateLayers ) static const LSET crt_yd( { B_CrtYd, F_CrtYd } ); static const LSET fab( { B_Fab, F_Fab } ); - LSET cu_board_mask = LSET::AllCuMask( m_board - ? m_board->GetCopperLayerCount() - : MAX_CU_LAYERS ); + LSET cu_board_mask = LSET::AllCuMask( m_board ? m_board->GetCopperLayerCount() : MAX_CU_LAYERS ); std::string output; diff --git a/pcbnew/pcb_io/odbpp/odb_entity.cpp b/pcbnew/pcb_io/odbpp/odb_entity.cpp index dcd85a302a..2bd87ae592 100644 --- a/pcbnew/pcb_io/odbpp/odb_entity.cpp +++ b/pcbnew/pcb_io/odbpp/odb_entity.cpp @@ -971,10 +971,9 @@ void ODB_STEP_ENTITY::MakeLayerEntity() for( PCB_LAYER_ID layer : pad_layers ) { - bool onCopperLayer = ( LSET::AllCuMask() & LSET( { layer } ) ).any(); - bool onSolderMaskLayer = ( LSET( { F_Mask, B_Mask } ) & LSET( { layer } ) ).any(); - bool onSolderPasteLayer = - ( LSET( { F_Paste, B_Paste } ) & LSET( { layer } ) ).any(); + bool onCopperLayer = LSET::AllCuMask().test( layer ); + bool onSolderMaskLayer = LSET( { F_Mask, B_Mask } ).test( layer ); + bool onSolderPasteLayer = LSET( { F_Paste, B_Paste } ).test( layer ); if( onSolderMaskLayer ) margin.x = margin.y = pad->GetSolderMaskExpansion( PADSTACK::ALL_LAYERS ); diff --git a/pcbnew/pcb_plot_params.cpp b/pcbnew/pcb_plot_params.cpp index ae76cb8935..d7aa414114 100644 --- a/pcbnew/pcb_plot_params.cpp +++ b/pcbnew/pcb_plot_params.cpp @@ -134,8 +134,7 @@ PCB_PLOT_PARAMS::PCB_PLOT_PARAMS() m_widthAdjust = 0.; m_textMode = PLOT_TEXT_MODE::DEFAULT; m_outputDirectory.clear(); - m_layerSelection = LSET( { F_SilkS, B_SilkS, F_Mask, B_Mask, - F_Paste, B_Paste, Edge_Cuts } ) + m_layerSelection = LSET( { F_SilkS, B_SilkS, F_Mask, B_Mask, F_Paste, B_Paste, Edge_Cuts } ) | LSET::AllCuMask(); m_PDFFrontFPPropertyPopups = true; diff --git a/pcbnew/pcb_track.cpp b/pcbnew/pcb_track.cpp index b57ab0dd75..81dfafae1b 100644 --- a/pcbnew/pcb_track.cpp +++ b/pcbnew/pcb_track.cpp @@ -1470,7 +1470,7 @@ std::vector PCB_VIA::ViewGetLayers() const LSET cuMask = LSET::AllCuMask(); if( const BOARD* board = GetBoard() ) - cuMask = board->GetEnabledLayers(); + cuMask &= board->GetEnabledLayers(); for( PCB_LAYER_ID layer : layers ) { diff --git a/pcbnew/specctra_import_export/specctra.cpp b/pcbnew/specctra_import_export/specctra.cpp index 2c842c7df7..a30256093d 100644 --- a/pcbnew/specctra_import_export/specctra.cpp +++ b/pcbnew/specctra_import_export/specctra.cpp @@ -80,7 +80,7 @@ void SPECCTRA_DB::buildLayerMaps( BOARD* aBoard ) // specctra wants top physical layer first, then going down to the // bottom most physical layer in physical sequence. - LSET layerset = aBoard->GetEnabledLayers() & LSET::AllCuMask(); + LSET layerset = LSET::AllCuMask( aBoard->GetCopperLayerCount() ); int pcbLayer = 0; for( PCB_LAYER_ID kiLayer : layerset.CuStack() ) diff --git a/pcbnew/specctra_import_export/specctra_export.cpp b/pcbnew/specctra_import_export/specctra_export.cpp index e2b6b2d42e..cc64294e99 100644 --- a/pcbnew/specctra_import_export/specctra_export.cpp +++ b/pcbnew/specctra_import_export/specctra_export.cpp @@ -248,9 +248,9 @@ PADSTACK* SPECCTRA_DB::makePADSTACK( BOARD* aBoard, PAD* aPad ) uniqifier = '['; - const int copperCount = aBoard->GetCopperLayerCount(); - static const LSET all_cu = LSET::AllCuMask( copperCount ); - int reportedLayers = 0; + const int copperCount = aBoard->GetCopperLayerCount(); + static const LSET all_cu = LSET::AllCuMask( copperCount ); + int reportedLayers = 0; std::vector layerName( copperCount ); bool onAllCopperLayers = ( (aPad->GetLayerSet() & all_cu) == all_cu ); @@ -258,7 +258,7 @@ PADSTACK* SPECCTRA_DB::makePADSTACK( BOARD* aBoard, PAD* aPad ) if( onAllCopperLayers ) uniqifier += 'A'; // A for all layers - for( int layer=0; layerGetEnabledLayers() & zone->GetLayerSet() & LSET::AllCuMask(); + LSET layerset = zone->GetLayerSet() & LSET::AllCuMask( aBoard->GetCopperLayerCount() ); for( PCB_LAYER_ID layer : layerset.CuStack() ) { @@ -1215,7 +1215,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) // Now, build zone polygon on each copper layer where the zone // is living (zones can live on many copper layers) - LSET layerset = aBoard->GetEnabledLayers() & zone->GetLayerSet() & LSET::AllCuMask(); + LSET layerset = zone->GetLayerSet() & LSET::AllCuMask( aBoard->GetCopperLayerCount() ); for( PCB_LAYER_ID layer : layerset ) { @@ -1339,7 +1339,7 @@ void SPECCTRA_DB::FromBOARD( BOARD* aBoard ) // Now, build keepout polygon on each copper layer where the zone // keepout is living (keepout zones can live on many copper layers) - LSET layerset = aBoard->GetEnabledLayers() & zone->GetLayerSet() & LSET::AllCuMask(); + LSET layerset = zone->GetLayerSet() & LSET::AllCuMask( aBoard->GetCopperLayerCount() ); for( PCB_LAYER_ID layer : layerset ) { diff --git a/pcbnew/tools/pcb_selection_tool.cpp b/pcbnew/tools/pcb_selection_tool.cpp index 142669784d..8591e4eb90 100644 --- a/pcbnew/tools/pcb_selection_tool.cpp +++ b/pcbnew/tools/pcb_selection_tool.cpp @@ -1485,11 +1485,9 @@ int PCB_SELECTION_TOOL::expandConnection( const TOOL_EVENT& aEvent ) } -void PCB_SELECTION_TOOL::selectAllConnectedTracks( - const std::vector& aStartItems, STOP_CONDITION aStopCondition ) +void PCB_SELECTION_TOOL::selectAllConnectedTracks( const std::vector& aStartItems, + STOP_CONDITION aStopCondition ) { - const LSET allCuMask = LSET::AllCuMask(); - PROF_TIMER refreshTimer; double refreshIntervalMs = 500; // Refresh display with this interval to indicate progress int lastSelectionSize = (int) m_selection.GetSize(); @@ -1612,7 +1610,7 @@ void PCB_SELECTION_TOOL::selectAllConnectedTracks( for( int i = (int) activePts.size() - 1; i >= 0; --i ) { VECTOR2I pt = activePts[i].first; - LSET layerSetCu = activePts[i].second & allCuMask; + LSET layerSetCu = activePts[i].second & LSET::AllCuMask(); auto viaIt = viaMap.find( pt ); auto padIt = padMap.find( pt ); diff --git a/pcbnew/tracks_cleaner.cpp b/pcbnew/tracks_cleaner.cpp index a2aaa1851b..63902dfa42 100644 --- a/pcbnew/tracks_cleaner.cpp +++ b/pcbnew/tracks_cleaner.cpp @@ -432,7 +432,7 @@ void TRACKS_CLEANER::cleanup( bool aDeleteDuplicateVias, bool aDeleteNullSegment // Examine the list of connected pads: if a through pad is found, the via is redundant for( PAD* pad : m_brd->GetConnectivity()->GetConnectedPads( via ) ) { - const LSET all_cu = LSET::AllCuMask(); + const LSET all_cu = LSET::AllCuMask( m_brd->GetCopperLayerCount() ); if( ( pad->GetLayerSet() & all_cu ) == all_cu ) { diff --git a/pcbnew/zone_filler.cpp b/pcbnew/zone_filler.cpp index c0aeecd829..07a34d704b 100644 --- a/pcbnew/zone_filler.cpp +++ b/pcbnew/zone_filler.cpp @@ -283,7 +283,7 @@ bool ZONE_FILLER::Fill( const std::vector& aZones, bool aCheck, wxWindow* footprint->BuildNetTieCache(); } - LSET boardCuMask = m_board->GetEnabledLayers() & LSET::AllCuMask(); + LSET boardCuMask = LSET::AllCuMask( m_board->GetCopperLayerCount() ); auto findHighestPriorityZone = [&]( const BOX2I& bbox, PCB_LAYER_ID itemLayer, int netcode, @@ -765,7 +765,7 @@ bool ZONE_FILLER::Fill( const std::vector& aZones, bool aCheck, wxWindow* // Don't check for connections on layers that only exist in the zone but // were disabled in the board BOARD* board = zone->GetBoard(); - LSET zoneCopperLayers = zone->GetLayerSet() & LSET::AllCuMask() & board->GetEnabledLayers(); + LSET zoneCopperLayers = zone->GetLayerSet() & LSET::AllCuMask( board->GetCopperLayerCount() ); // Min-thickness is the web thickness. On the other hand, a blob min-thickness by // min-thickness is not useful. Since there's no obvious definition of web vs. blob, we