diff --git a/pcbnew/board_stackup_manager/board_stackup.cpp b/pcbnew/board_stackup_manager/board_stackup.cpp index fb08d87a33..56b55722ff 100644 --- a/pcbnew/board_stackup_manager/board_stackup.cpp +++ b/pcbnew/board_stackup_manager/board_stackup.cpp @@ -840,7 +840,6 @@ int BOARD_STACKUP::GetLayerDistance( PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSec int total = 0; bool start = false; - bool half = false; for( BOARD_STACKUP_ITEM* item : m_list ) { @@ -852,25 +851,15 @@ int BOARD_STACKUP::GetLayerDistance( PCB_LAYER_ID aFirstLayer, PCB_LAYER_ID aSec // Reached the start copper layer? Start counting the next dielectric after it if( !start && ( layer != UNDEFINED_LAYER && layer == aFirstLayer ) ) - { start = true; - half = true; - } else if( !start ) continue; - // Reached the stop copper layer? we're done - if( start && ( layer != UNDEFINED_LAYER && layer == aSecondLayer ) ) - half = true; - for( int sublayer = 0; sublayer < item->GetSublayersCount(); sublayer++ ) { - int subThickness = item->GetThickness( sublayer ); - total += half ? ( subThickness / 2 ) : subThickness; + total += item->GetThickness( sublayer ); } - half = false; - if( layer != UNDEFINED_LAYER && layer == aSecondLayer ) break; } diff --git a/qa/data/pcbnew/length_calculations.kicad_dru b/qa/data/pcbnew/length_calculations.kicad_dru index 8adaf60be1..8fab3269d7 100644 --- a/qa/data/pcbnew/length_calculations.kicad_dru +++ b/qa/data/pcbnew/length_calculations.kicad_dru @@ -7,17 +7,17 @@ (rule "CASE_2" (condition "A.hasNetclass('CASE_2')") - (constraint length (min 14.8795mm) (max 14.8805mm)) + (constraint length (min 14.9145mm) (max 14.9155mm)) ) (rule "CASE_3" (condition "A.hasNetclass('CASE_3')") - (constraint length (min 14.8795mm) (max 14.8805mm)) + (constraint length (min 14.9145mm) (max 14.9155mm)) ) (rule "CASE_4" (condition "A.hasNetclass('CASE_4')") - (constraint length (min 16.4245mm) (max 16.4250mm)) + (constraint length (min 16.4945mm) (max 16.4955mm)) ) (rule "CASE_5" diff --git a/qa/data/pcbnew/length_calculations.kicad_pcb b/qa/data/pcbnew/length_calculations.kicad_pcb index 55fb86952b..45a7acf3e5 100644 --- a/qa/data/pcbnew/length_calculations.kicad_pcb +++ b/qa/data/pcbnew/length_calculations.kicad_pcb @@ -1,5 +1,5 @@ (kicad_pcb - (version 20250324) + (version 20250801) (generator "pcbnew") (generator_version "9.99") (general @@ -97,15 +97,12 @@ (usegerberattributes yes) (usegerberadvancedattributes yes) (creategerberjobfile yes) - (dashed_line_dash_ratio 12.000000) - (dashed_line_gap_ratio 3.000000) + (dashed_line_dash_ratio 12) + (dashed_line_gap_ratio 3) (svgprecision 4) (plotframeref no) (mode 1) (useauxorigin no) - (hpglpennumber 1) - (hpglpenspeed 20) - (hpglpendiameter 15.000000) (pdf_front_fp_property_popups yes) (pdf_back_fp_property_popups yes) (pdf_metadata yes) @@ -2725,7 +2722,7 @@ (justify left bottom) ) ) - (gr_text "Single track from pad to pad, with pad in via.\nLength 14.880mm (13.3350mm track, 1.545mm via)" + (gr_text "Single track from pad to pad, with pad in via.\nLength 14.9150mm (13.3350mm track, 1.5800mm via)" (at 140.335 55.118 0) (layer "User.1") (uuid "7f83c8bc-048a-4517-931d-402bdaf6d0dd") @@ -2737,7 +2734,7 @@ (justify left bottom) ) ) - (gr_text "Track from pad to pad with two vias in track.\nLength 16.4250mm (13.3350mm track, 3.0900mm via)" + (gr_text "Track from pad to pad with two vias in track.\nLength 16.4950mm (13.3350mm track, 3.1600mm via)" (at 140.335 66.04 0) (layer "User.1") (uuid "f5fbb9e1-572a-4383-ab51-2db44f23ce1d") @@ -2749,7 +2746,7 @@ (justify left bottom) ) ) - (gr_text "Track from pad to pad with via in track.\nLength 14.880mm (13.3350mm track, 1.545mm via)" + (gr_text "Track from pad to pad with via in track.\nLength 14.9150mm (13.3350mm track, 1.5800mm via)" (at 140.335 60.706 0) (layer "User.1") (uuid "f95e887a-6964-4b75-a74b-933d6fa74a59") diff --git a/qa/data/pcbnew/length_calculations.kicad_pro b/qa/data/pcbnew/length_calculations.kicad_pro index 4ccbdeefeb..06c0419ec9 100644 --- a/qa/data/pcbnew/length_calculations.kicad_pro +++ b/qa/data/pcbnew/length_calculations.kicad_pro @@ -478,13 +478,14 @@ "priority": 2147483647, "schematic_color": "rgba(0, 0, 0, 0.000)", "track_width": 0.2, + "tuning_profile": "", "via_diameter": 0.6, "via_drill": 0.3, "wire_width": 6 } ], "meta": { - "version": 4 + "version": 5 }, "net_colors": null, "netclass_assignments": { @@ -654,5 +655,11 @@ "Root" ] ], - "text_variables": {} + "text_variables": {}, + "time_domain_parameters": { + "delay_profiles_user_defined": [], + "meta": { + "version": 0 + } + } } diff --git a/qa/data/pcbnew/time_calculations.kicad_dru b/qa/data/pcbnew/time_calculations.kicad_dru index 74b4e810a0..3aa1df431a 100644 --- a/qa/data/pcbnew/time_calculations.kicad_dru +++ b/qa/data/pcbnew/time_calculations.kicad_dru @@ -17,7 +17,7 @@ (rule CLASS4 (condition "A.hasNetclass('CLASS4')") - (constraint length (min 31.38ps) (opt 31.39ps) (max 31.40ps)) + (constraint length (min 31.42ps) (opt 31.43ps) (max 31.44ps)) ) (rule CLASS5 diff --git a/qa/data/pcbnew/time_calculations.kicad_pcb b/qa/data/pcbnew/time_calculations.kicad_pcb index c2ef88bca4..083dfe3770 100644 --- a/qa/data/pcbnew/time_calculations.kicad_pcb +++ b/qa/data/pcbnew/time_calculations.kicad_pcb @@ -1,5 +1,5 @@ (kicad_pcb - (version 20250401) + (version 20250801) (generator "pcbnew") (generator_version "9.99") (general @@ -121,15 +121,12 @@ (usegerberattributes yes) (usegerberadvancedattributes yes) (creategerberjobfile yes) - (dashed_line_dash_ratio 12.000000) - (dashed_line_gap_ratio 3.000000) + (dashed_line_dash_ratio 12) + (dashed_line_gap_ratio 3) (svgprecision 4) (plotframeref no) (mode 1) (useauxorigin no) - (hpglpennumber 1) - (hpglpenspeed 20) - (hpglpendiameter 15.000000) (pdf_front_fp_property_popups yes) (pdf_back_fp_property_popups yes) (pdf_metadata yes) @@ -3552,7 +3549,7 @@ (justify left bottom) ) ) - (gr_text "Two layer track + via\nT = 31.39ps" + (gr_text "Two layer track + via\nT = 31.43ps" (at 128.905 71.12 0) (layer "User.1") (uuid "2942d426-2cfc-4054-86e6-b3cc0ace1bbc")