From 8985ee05fa5e7b993ea7cb520416d546e6610200 Mon Sep 17 00:00:00 2001
From: Mark Roszko <mark.roszko@gmail.com>
Date: Fri, 5 Dec 2025 23:15:01 -0500
Subject: [PATCH] Add missing allegro/pads qa

---
 .../cli/basic_test/basic_test.netlist.allegro | 40 +++++++++++++++++++
 .../cli/basic_test/basic_test.netlist.pads    | 26 ++++++++++++
 qa/tests/cli/test_sch.py                      |  4 +-
 3 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 qa/data/cli/basic_test/basic_test.netlist.allegro
 create mode 100644 qa/data/cli/basic_test/basic_test.netlist.pads

diff --git a/qa/data/cli/basic_test/basic_test.netlist.allegro b/qa/data/cli/basic_test/basic_test.netlist.allegro
new file mode 100644
index 0000000000..3990ebcb1c
--- /dev/null
+++ b/qa/data/cli/basic_test/basic_test.netlist.allegro
@@ -0,0 +1,40 @@
+(NETLIST)
+(Source: E:\kicad\kicad\qa\data\cli\basic_test\basic_test.kicad_sch)
+(Date: 2025-12-05T23:11:58-0500)
+$PACKAGES
+! '10k_resistor_smd_r_1206_3216metric' ! '10k' ; R1,
+	R2
+! '10u_capacitor_smd_c_1206_3216metric' ! '10u' ; C1
+! 'conn_01x01_pin_testpoint_testpoint_pad_3_0x3_0mm' ! 'Conn_01x01_Pin' ; J1,
+	J2,
+	J4
+! 'tlv2371dbv_package_to_sot_smd_sot-23-5' ! 'TLV2371DBV' ; U1
+$A_PROPERTIES
+'ROOM' '/' ; C1,
+	J1,
+	J2,
+	J3,
+	J4,
+	R1,
+	R2,
+	R3,
+	U1
+$NETS
+/IN; J2.1,
+	R3.1
+/OUT; J3.1,
+	R2.2,
+	U1.1
+/VCC; J1.1,
+	U1.5
+GND; C1.2,
+	J4.1,
+	R1.1,
+	U1.2
+'NET-(U1-+)'; C1.1,
+	R3.2,
+	U1.3
+'NET-(U1--)'; R1.2,
+	R2.1,
+	U1.4
+$END
diff --git a/qa/data/cli/basic_test/basic_test.netlist.pads b/qa/data/cli/basic_test/basic_test.netlist.pads
new file mode 100644
index 0000000000..a8cd70ae03
--- /dev/null
+++ b/qa/data/cli/basic_test/basic_test.netlist.pads
@@ -0,0 +1,26 @@
+*PADS-PCB*
+*PART*
+R1               Resistor_SMD:R_1206_3216Metric
+C1               Capacitor_SMD:C_1206_3216Metric
+R2               Resistor_SMD:R_1206_3216Metric
+J3               TestPoint:TestPoint_Pad_3.0x3.0mm
+J2               TestPoint:TestPoint_Pad_3.0x3.0mm
+J1               TestPoint:TestPoint_Pad_3.0x3.0mm
+J4               TestPoint:TestPoint_Pad_3.0x3.0mm
+R3               Resistor_SMD:R_1206_3216Metric
+U1               Package_TO_SOT_SMD:SOT-23-5
+
+*NET*
+*SIGNAL* /OUT
+J3.1 R2.2 U1.1 
+*SIGNAL* /VCC
+J1.1 U1.5 
+*SIGNAL* Net-(U1-+)
+C1.1 R3.2 U1.3 
+*SIGNAL* Net-(U1--)
+R1.2 R2.1 U1.4 
+*SIGNAL* GND
+C1.2 J4.1 R1.1 U1.2 
+*SIGNAL* /IN
+J2.1 R3.1 
+*END*
diff --git a/qa/tests/cli/test_sch.py b/qa/tests/cli/test_sch.py
index f5cfe488de..98889b90dd 100644
--- a/qa/tests/cli/test_sch.py
+++ b/qa/tests/cli/test_sch.py
@@ -80,7 +80,9 @@ def test_sch_export_svg( kitest,
                              ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.kicadsexpr", 5, True,["--format=kicadsexpr"]),
                              ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.kicadxml", 6, True,["--format=kicadxml"]),
                              ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.cadstar", 3, False, ["--format=cadstar"]),
-                             ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.orcadpcb2", 1, False, ["--format=orcadpcb2"])
+                             ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.orcadpcb2", 1, False, ["--format=orcadpcb2"]),
+                             ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.pads", 0, False, ["--format=pads"]),
+                             ("cli/basic_test/basic_test.kicad_sch", "basic_test.netlist.allegro", 3, False, ["--format=allegro"]),
                              ])
 def test_sch_export_netlist( kitest,
                              test_file: str,