Multi-netclass support

pcbnew/python/scripting/pcbnew_scripting_helpers.cpp

@@ -246,7 +246,7 @@ BOARD* LoadBoard( wxString& aFileName, PCB_IO_MGR::PCB_FILE_T aFormat, bool aSet
 
         brd->BuildConnectivity();
         brd->BuildListOfNets();
-        brd->SynchronizeNetsAndNetClasses( false );
+        brd->SynchronizeNetsAndNetClasses( true );
         brd->UpdateUserUnits( brd, nullptr );
     }
 

pcbnew/python/swig/board.i

@@ -154,7 +154,7 @@ HANDLE_EXCEPTIONS(BOARD::TracksInNetBetweenPoints)
         return SaveBoard(filename,self)
 
     def GetNetClasses(self):
-        return self.GetDesignSettings().m_NetSettings.m_NetClasses
+        return self.GetDesignSettings().m_NetSettings.GetNetclasses()
 
     def GetCurrentNetClassName(self):
         return self.GetDesignSettings().GetCurrentNetClassName()
@@ -194,7 +194,7 @@ HANDLE_EXCEPTIONS(BOARD::TracksInNetBetweenPoints)
         # Copy the NETCLASS_MAP so the one in the BOARD isn't modified
         # when we add the Default net class.
         netclassmap = {k:v for k,v in self.GetNetClasses().items()}
-        netclassmap['Default'] = self.GetDesignSettings().m_NetSettings.m_DefaultNetClass
+        netclassmap['Default'] = self.GetDesignSettings().m_NetSettings.GetDefaultNetclass()
         return netclassmap
     %}
 }

pcbnew/python/swig/board_design_settings.i

@@ -1,7 +1,7 @@
 %ignore BOARD_DESIGN_SETTINGS::m_Pad_Master;
 %ignore BOARD_DESIGN_SETTINGS::m_DRCEngine;
-%ignore NET_SETTINGS::m_NetClassPatternAssignments;
-%ignore NET_SETTINGS::m_NetClassLabelAssignments;
+%ignore NET_SETTINGS::m_netClassPatternAssignments;
+%ignore NET_SETTINGS::m_netClassLabelAssignments;
 
 %shared_ptr(NET_SETTINGS)
 %template(netclasses_map) std::map<wxString, std::shared_ptr<NETCLASS>>;