Eeschema: improve simulator behavior for two-source DC analysis
Fixes: lp:1830478
* https://bugs.launchpad.net/kicad/+bug/1830478
(cherry picked from commit 356ccd0314)
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@@ -620,6 +620,49 @@ bool SIM_PLOT_FRAME::updatePlot( const TRACE_DESC& aDescriptor, SIM_PLOT_PANEL*
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if( data_y.size() != size )
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return false;
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// If we did a two-source DC analysis, we need to split the resulting vector and add traces
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// for each input step
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SPICE_DC_PARAMS source1, source2;
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if( m_exporter->GetSimType() == ST_DC &&
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m_exporter->ParseDCCommand( m_exporter->GetUsedSimCommand(), &source1, &source2 ) )
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{
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if( !source2.m_source.IsEmpty() )
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{
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// Source 1 is the inner loop, so lets add traces for each Source 2 (outer loop) step
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SPICE_VALUE v = source2.m_vstart;
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wxString name;
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size_t offset = 0;
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size_t outer = ( size_t )( ( source2.m_vend - v ) / source2.m_vincrement ).ToDouble();
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size_t inner = data_x.size() / ( outer + 1 );
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wxASSERT( data_x.size() % ( outer + 1 ) == 0 );
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for( size_t idx = 0; idx <= outer; idx++ )
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{
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name = wxString::Format( "%s (%s = %s V)", aDescriptor.GetTitle(),
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source2.m_source, v.ToString() );
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std::vector<double> sub_x( data_x.begin() + offset,
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data_x.begin() + offset + inner );
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std::vector<double> sub_y( data_y.begin() + offset,
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data_y.begin() + offset + inner );
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if( aPanel->AddTrace( name, inner,
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sub_x.data(), sub_y.data(), aDescriptor.GetType() ) )
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{
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m_plots[aPanel].m_traces.insert( std::make_pair( name, aDescriptor ) );
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}
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v = v + source2.m_vincrement;
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offset += inner;
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}
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return true;
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}
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}
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if( aPanel->AddTrace( aDescriptor.GetTitle(), size,
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data_x.data(), data_y.data(), aDescriptor.GetType() ) )
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{
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