diff --git a/common/bitmap_info.cpp b/common/bitmap_info.cpp index 42173d3867..59f97073b3 100644 --- a/common/bitmap_info.cpp +++ b/common/bitmap_info.cpp @@ -5042,7 +5042,7 @@ void BuildBitmapInfo( std::unordered_map>& aBi aBitmapInfoCache[BITMAPS::constraint_minimum_annular_width].emplace_back( BITMAPS::constraint_minimum_annular_width, wxT( "constraint_minimum_annular_width.png" ), -1, wxT( "light" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_clearance].emplace_back( BITMAPS::constraint_minimum_clearance, wxT( "constraint_minimum_clearance.png" ), -1, wxT( "light" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_connection_width].emplace_back( BITMAPS::constraint_minimum_connection_width, wxT( "constraint_minimum_connection_width.png" ), -1, wxT( "light" ) ); - aBitmapInfoCache[BITMAPS::constraint_minimum_item_clearance].emplace_back( BITMAPS::constraint_minimum_item_clearance, wxT( "constraint_minimum_item_clearance.png" ), -1, wxT( "light" ) ); + aBitmapInfoCache[BITMAPS::constraint_silk_to_silk_clearance].emplace_back( BITMAPS::constraint_silk_to_silk_clearance, wxT( "constraint_silk_to_silk_clearance.png" ), -1, wxT( "light" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_soldermask_silver].emplace_back( BITMAPS::constraint_minimum_soldermask_silver, wxT( "constraint_minimum_soldermask_silver.png" ), -1, wxT( "light" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_text_height_and_thickness].emplace_back( BITMAPS::constraint_minimum_text_height_and_thickness, wxT( "constraint_minimum_text_height_and_thickness.png" ), -1, wxT( "light" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_thermal_relief_spoke_count].emplace_back( BITMAPS::constraint_minimum_thermal_relief_spoke_count, wxT( "constraint_minimum_thermal_relief_spoke_count.png" ), -1, wxT( "light" ) ); @@ -5079,7 +5079,7 @@ void BuildBitmapInfo( std::unordered_map>& aBi aBitmapInfoCache[BITMAPS::constraint_minimum_annular_width].emplace_back( BITMAPS::constraint_minimum_annular_width, wxT( "constraint_minimum_annular_width_dark.png" ), -1, wxT( "dark" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_clearance].emplace_back( BITMAPS::constraint_minimum_clearance, wxT( "constraint_minimum_clearance_dark.png" ), -1, wxT( "dark" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_connection_width].emplace_back( BITMAPS::constraint_minimum_connection_width, wxT( "constraint_minimum_connection_width_dark.png" ), -1, wxT( "dark" ) ); - aBitmapInfoCache[BITMAPS::constraint_minimum_item_clearance].emplace_back( BITMAPS::constraint_minimum_item_clearance, wxT( "constraint_minimum_item_clearance_dark.png" ), -1, wxT( "dark" ) ); + aBitmapInfoCache[BITMAPS::constraint_silk_to_silk_clearance].emplace_back( BITMAPS::constraint_silk_to_silk_clearance, wxT( "constraint_silk_to_silk_clearance_dark.png" ), -1, wxT( "dark" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_soldermask_silver].emplace_back( BITMAPS::constraint_minimum_soldermask_silver, wxT( "constraint_minimum_soldermask_silver_dark.png" ), -1, wxT( "dark" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_text_height_and_thickness].emplace_back( BITMAPS::constraint_minimum_text_height_and_thickness, wxT( "constraint_minimum_text_height_and_thickness_dark.png" ), -1, wxT( "dark" ) ); aBitmapInfoCache[BITMAPS::constraint_minimum_thermal_relief_spoke_count].emplace_back( BITMAPS::constraint_minimum_thermal_relief_spoke_count, wxT( "constraint_minimum_thermal_relief_spoke_count_dark.png" ), -1, wxT( "dark" ) ); diff --git a/include/bitmaps/bitmaps_list.h b/include/bitmaps/bitmaps_list.h index 3c41250002..bf90327646 100644 --- a/include/bitmaps/bitmaps_list.h +++ b/include/bitmaps/bitmaps_list.h @@ -697,7 +697,7 @@ enum class BITMAPS : unsigned int constraint_minimum_clearance, constraint_creepage_distance, constraint_minimum_connection_width, - constraint_minimum_item_clearance, + constraint_silk_to_silk_clearance, constraint_minimum_track_width, constraint_copper_to_hole_clearance, constraint_hole_to_hole_clearance, diff --git a/pcbnew/drc/rule_editor/dialog_drc_rule_editor.cpp b/pcbnew/drc/rule_editor/dialog_drc_rule_editor.cpp index c1cb9dd199..51d8c656c4 100644 --- a/pcbnew/drc/rule_editor/dialog_drc_rule_editor.cpp +++ b/pcbnew/drc/rule_editor/dialog_drc_rule_editor.cpp @@ -597,14 +597,8 @@ std::vector DIALOG_DRC_RULE_EDITOR::buildElectricalRuleTreeNodes result.push_back( buildRuleTreeNodeData( "Clearance", DRC_RULE_EDITOR_ITEM_TYPE::CATEGORY, aParentId ) ); lastParentId = m_nodeId; - result.push_back( buildRuleTreeNodeData( "Basic clearance", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, lastParentId, - BASIC_CLEARANCE ) ); - result.push_back( buildRuleTreeNodeData( "Board outline clearance", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, - lastParentId, BOARD_OUTLINE_CLEARANCE ) ); result.push_back( buildRuleTreeNodeData( "Minimum clearance", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, lastParentId, MINIMUM_CLEARANCE ) ); - result.push_back( buildRuleTreeNodeData( "Minimum item clearance", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, - lastParentId, MINIMUM_ITEM_CLEARANCE ) ); result.push_back( buildRuleTreeNodeData( "Copper to edge clearance", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, lastParentId, COPPER_TO_EDGE_CLEARANCE ) ); result.push_back( buildRuleTreeNodeData( "Courtyard Clearance", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, lastParentId, @@ -619,8 +613,6 @@ std::vector DIALOG_DRC_RULE_EDITOR::buildElectricalRuleTreeNodes result.push_back( buildRuleTreeNodeData( "Minimum connection width", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, lastParentId, MINIMUM_CONNECTION_WIDTH ) ); - result.push_back( buildRuleTreeNodeData( "Minimum track width", DRC_RULE_EDITOR_ITEM_TYPE::CONSTRAINT, lastParentId, - MINIMUM_TRACK_WIDTH ) ); result.push_back( buildRuleTreeNodeData( "Hole Clearance", DRC_RULE_EDITOR_ITEM_TYPE::CATEGORY, aParentId ) ); lastParentId = m_nodeId; diff --git a/pcbnew/drc/rule_editor/drc_re_numeric_constraint_types.h b/pcbnew/drc/rule_editor/drc_re_numeric_constraint_types.h index 1ee042f935..f44e2ba117 100644 --- a/pcbnew/drc/rule_editor/drc_re_numeric_constraint_types.h +++ b/pcbnew/drc/rule_editor/drc_re_numeric_constraint_types.h @@ -27,29 +27,6 @@ #include "drc_re_numeric_input_constraint_data.h" #include "drc_re_overlay_types.h" -class DRC_RE_BASIC_CLEARANCE_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA -{ -public: - using DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA::DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA; - BITMAPS GetOverlayBitmap() const override { return BITMAPS::constraint_basic_clearance; } - std::vector GetFieldPositions() const override - { - return { { 160, 190, 202, 1, wxS( "mm" ), LABEL_POSITION::RIGHT } }; - } -}; - - -class DRC_RE_BOARD_OUTLINE_CLEARANCE_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA -{ -public: - using DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA::DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA; - BITMAPS GetOverlayBitmap() const override { return BITMAPS::constraint_board_outline_clearance; } - std::vector GetFieldPositions() const override - { - return { { 185, 215, 207, 1, wxS( "mm" ), LABEL_POSITION::RIGHT } }; - } -}; - class DRC_RE_COPPER_TO_EDGE_CLEARANCE_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA { @@ -211,18 +188,6 @@ public: }; -class DRC_RE_MINIMUM_ITEM_CLEARANCE_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA -{ -public: - using DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA::DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA; - BITMAPS GetOverlayBitmap() const override { return BITMAPS::constraint_minimum_item_clearance; } - std::vector GetFieldPositions() const override - { - return { { 190, 220, 92, 1, wxS( "mm" ), LABEL_POSITION::RIGHT } }; - } -}; - - class DRC_RE_MINIMUM_SOLDERMASK_SILVER_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA { public: @@ -255,16 +220,6 @@ public: } }; -class DRC_RE_MINIMUM_TRACK_WIDTH_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA -{ -public: - using DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA::DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA; - BITMAPS GetOverlayBitmap() const override { return BITMAPS::constraint_minimum_track_width; } - std::vector GetFieldPositions() const override - { - return { { 205, 235, 112, 1, wxS( "mm" ), LABEL_POSITION::RIGHT } }; - } -}; class DRC_RE_MINIMUM_UVIA_DIAMETER_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA { @@ -304,10 +259,10 @@ class DRC_RE_SILK_TO_SILK_CLEARANCE_CONSTRAINT_DATA : public DRC_RE_NUMERIC_INPU { public: using DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA::DRC_RE_NUMERIC_INPUT_CONSTRAINT_DATA; - BITMAPS GetOverlayBitmap() const override { return BITMAPS::constraint_silk_clearance; } + BITMAPS GetOverlayBitmap() const override { return BITMAPS::constraint_silk_to_silk_clearance; } std::vector GetFieldPositions() const override { - return { { 85, 105, 58, 1, wxS( "mm" ), LABEL_POSITION::RIGHT } }; + return { { 232, 272, 92, 1, wxS( "mm" ), LABEL_POSITION::RIGHT } }; } }; diff --git a/pcbnew/drc/rule_editor/drc_re_panel_matcher.cpp b/pcbnew/drc/rule_editor/drc_re_panel_matcher.cpp index b2e0c30855..290ffce0a7 100644 --- a/pcbnew/drc/rule_editor/drc_re_panel_matcher.cpp +++ b/pcbnew/drc/rule_editor/drc_re_panel_matcher.cpp @@ -166,13 +166,13 @@ void DRC_PANEL_MATCHER::initClaims() // Size constraints m_claims.emplace_back( - MINIMUM_THROUGH_HOLE, + HOLE_SIZE, std::set{ HOLE_SIZE_CONSTRAINT }, std::set{}, 20 ); m_claims.emplace_back( - MINIMUM_UVIA_DIAMETER, + MINIMUM_VIA_DIAMETER, std::set{ VIA_DIAMETER_CONSTRAINT }, std::set{}, 20 ); diff --git a/pcbnew/drc/rule_editor/drc_re_rule_loader.cpp b/pcbnew/drc/rule_editor/drc_re_rule_loader.cpp index 95fd735edb..63043e8011 100644 --- a/pcbnew/drc/rule_editor/drc_re_rule_loader.cpp +++ b/pcbnew/drc/rule_editor/drc_re_rule_loader.cpp @@ -156,20 +156,6 @@ DRC_RULE_LOADER::createConstraintData( DRC_RULE_EDITOR_CONSTRAINT_NAME aPanel, return data; } - case MINIMUM_TRACK_WIDTH: - { - auto data = std::make_shared(); - data->SetRuleName( aRule.m_Name ); - data->SetConstraintCode( "track_width" ); - - const DRC_CONSTRAINT* constraint = findConstraint( aRule, TRACK_WIDTH_CONSTRAINT ); - - if( constraint ) - data->SetNumericInputValue( toMM( constraint->GetValue().Min() ) ); - - return data; - } - case ROUTING_WIDTH: { auto data = std::make_shared(); @@ -373,14 +359,6 @@ std::vector DRC_RULE_LOADER::LoadRule( const DRC_RULE } } - if( match.panelType == ROUTING_WIDTH && match.claimedConstraints.count( TRACK_WIDTH_CONSTRAINT ) ) - { - const DRC_CONSTRAINT* tw = findConstraint( aRule, TRACK_WIDTH_CONSTRAINT ); - - if( tw && !tw->GetValue().HasOpt() && !tw->GetValue().HasMax() ) - match.panelType = MINIMUM_TRACK_WIDTH; - } - auto constraintData = createConstraintData( match.panelType, aRule, match.claimedConstraints ); if( constraintData ) diff --git a/pcbnew/drc/rule_editor/drc_rule_editor_enums.h b/pcbnew/drc/rule_editor/drc_rule_editor_enums.h index 98d233af35..6fdcc10f8e 100644 --- a/pcbnew/drc/rule_editor/drc_rule_editor_enums.h +++ b/pcbnew/drc/rule_editor/drc_rule_editor_enums.h @@ -75,13 +75,9 @@ enum DRC_RULE_EDITOR_ITEM_TYPE enum DRC_RULE_EDITOR_CONSTRAINT_NAME { - BASIC_CLEARANCE = 0, - BOARD_OUTLINE_CLEARANCE, - MINIMUM_CLEARANCE, - MINIMUM_ITEM_CLEARANCE, + MINIMUM_CLEARANCE = 0, CREEPAGE_DISTANCE, MINIMUM_CONNECTION_WIDTH, - MINIMUM_TRACK_WIDTH, COPPER_TO_HOLE_CLEARANCE, HOLE_TO_HOLE_CLEARANCE, MINIMUM_THERMAL_RELIEF_SPOKE_COUNT, diff --git a/pcbnew/drc/rule_editor/drc_rule_editor_utils.cpp b/pcbnew/drc/rule_editor/drc_rule_editor_utils.cpp index 78c8f0e9a8..83c3cf2029 100644 --- a/pcbnew/drc/rule_editor/drc_rule_editor_utils.cpp +++ b/pcbnew/drc/rule_editor/drc_rule_editor_utils.cpp @@ -46,13 +46,9 @@ using CODE_MAP = std::unordered_map; using REVERSE_CODE_MAP = std::unordered_map; -static const CODE_MAP sCodeMap = { { BASIC_CLEARANCE, "clearance" }, - { BOARD_OUTLINE_CLEARANCE, "edge_clearance" }, - { MINIMUM_CLEARANCE, "clearance" }, - { MINIMUM_ITEM_CLEARANCE, "clearance" }, +static const CODE_MAP sCodeMap = { { MINIMUM_CLEARANCE, "clearance" }, { CREEPAGE_DISTANCE, "creepage" }, { MINIMUM_CONNECTION_WIDTH, "connection_width" }, - { MINIMUM_TRACK_WIDTH, "track_width" }, { COPPER_TO_HOLE_CLEARANCE, "hole_clearance" }, { HOLE_TO_HOLE_CLEARANCE, "hole_to_hole" }, { MINIMUM_THERMAL_RELIEF_SPOKE_COUNT, "min_resolved_spokes" }, @@ -280,8 +276,6 @@ bool DRC_RULE_EDITOR_UTILS::IsNumericInputType( const DRC_RULE_EDITOR_CONSTRAINT { switch( aConstraintType ) { - case BASIC_CLEARANCE: - case BOARD_OUTLINE_CLEARANCE: case COPPER_TO_EDGE_CLEARANCE: case COPPER_TO_HOLE_CLEARANCE: case COURTYARD_CLEARANCE: @@ -297,11 +291,9 @@ bool DRC_RULE_EDITOR_UTILS::IsNumericInputType( const DRC_RULE_EDITOR_CONSTRAINT case MINIMUM_ANNULAR_WIDTH: case MINIMUM_CLEARANCE: case MINIMUM_CONNECTION_WIDTH: - case MINIMUM_ITEM_CLEARANCE: case MINIMUM_SOLDERMASK_SILVER: case MINIMUM_THERMAL_RELIEF_SPOKE_COUNT: case MINIMUM_THROUGH_HOLE: - case MINIMUM_TRACK_WIDTH: case MINIMUM_UVIA_DIAMETER: case MINIMUM_UVIA_HOLE: case MINIMUM_VIA_DIAMETER: @@ -797,9 +789,7 @@ DRC_LAYER_CATEGORY DRC_RULE_EDITOR_UTILS::GetLayerCategoryForConstraint( switch( aConstraintType ) { // COPPER_ONLY: Constraints that only apply to copper layers - case BASIC_CLEARANCE: case MINIMUM_CLEARANCE: - case MINIMUM_ITEM_CLEARANCE: case CREEPAGE_DISTANCE: case COPPER_TO_HOLE_CLEARANCE: case COPPER_TO_EDGE_CLEARANCE: @@ -808,7 +798,6 @@ DRC_LAYER_CATEGORY DRC_RULE_EDITOR_UTILS::GetLayerCategoryForConstraint( case MINIMUM_UVIA_DIAMETER: case MINIMUM_UVIA_HOLE: case MINIMUM_ANNULAR_WIDTH: - case MINIMUM_TRACK_WIDTH: case MINIMUM_CONNECTION_WIDTH: case ROUTING_WIDTH: case ROUTING_DIFF_PAIR: @@ -838,7 +827,6 @@ DRC_LAYER_CATEGORY DRC_RULE_EDITOR_UTILS::GetLayerCategoryForConstraint( return DRC_LAYER_CATEGORY::TOP_BOTTOM_ANY; // GENERAL_ANY_LAYER: Constraints that can apply to any layer type - case BOARD_OUTLINE_CLEARANCE: case HOLE_TO_HOLE_CLEARANCE: case PHYSICAL_CLEARANCE: case HOLE_SIZE: @@ -891,8 +879,6 @@ DRC_RULE_EDITOR_UTILS::CreateNumericConstraintData( DRC_RULE_EDITOR_CONSTRAINT_N { switch( aType ) { - case BASIC_CLEARANCE: return std::make_shared(); - case BOARD_OUTLINE_CLEARANCE: return std::make_shared(); case COPPER_TO_EDGE_CLEARANCE: return std::make_shared(); case COPPER_TO_HOLE_CLEARANCE: return std::make_shared(); case COURTYARD_CLEARANCE: return std::make_shared(); @@ -907,11 +893,9 @@ DRC_RULE_EDITOR_UTILS::CreateNumericConstraintData( DRC_RULE_EDITOR_CONSTRAINT_N case MINIMUM_ANNULAR_WIDTH: return std::make_shared(); case MINIMUM_CLEARANCE: return std::make_shared(); case MINIMUM_CONNECTION_WIDTH: return std::make_shared(); - case MINIMUM_ITEM_CLEARANCE: return std::make_shared(); case MINIMUM_SOLDERMASK_SILVER: return std::make_shared(); case MINIMUM_THERMAL_RELIEF_SPOKE_COUNT: return std::make_shared(); case MINIMUM_THROUGH_HOLE: return std::make_shared(); - case MINIMUM_TRACK_WIDTH: return std::make_shared(); case MINIMUM_UVIA_DIAMETER: return std::make_shared(); case MINIMUM_UVIA_HOLE: return std::make_shared(); case MINIMUM_VIA_DIAMETER: return std::make_shared(); @@ -930,8 +914,6 @@ DRC_RULE_EDITOR_UTILS::CreateNumericConstraintData( DRC_RULE_EDITOR_CONSTRAINT_N { switch( aType ) { - case BASIC_CLEARANCE: return std::make_shared( aBase ); - case BOARD_OUTLINE_CLEARANCE: return std::make_shared( aBase ); case COPPER_TO_EDGE_CLEARANCE: return std::make_shared( aBase ); case COPPER_TO_HOLE_CLEARANCE: return std::make_shared( aBase ); case COURTYARD_CLEARANCE: return std::make_shared( aBase ); @@ -946,11 +928,9 @@ DRC_RULE_EDITOR_UTILS::CreateNumericConstraintData( DRC_RULE_EDITOR_CONSTRAINT_N case MINIMUM_ANNULAR_WIDTH: return std::make_shared( aBase ); case MINIMUM_CLEARANCE: return std::make_shared( aBase ); case MINIMUM_CONNECTION_WIDTH: return std::make_shared( aBase ); - case MINIMUM_ITEM_CLEARANCE: return std::make_shared( aBase ); case MINIMUM_SOLDERMASK_SILVER: return std::make_shared( aBase ); case MINIMUM_THERMAL_RELIEF_SPOKE_COUNT: return std::make_shared( aBase ); case MINIMUM_THROUGH_HOLE: return std::make_shared( aBase ); - case MINIMUM_TRACK_WIDTH: return std::make_shared( aBase ); case MINIMUM_UVIA_DIAMETER: return std::make_shared( aBase ); case MINIMUM_UVIA_HOLE: return std::make_shared( aBase ); case MINIMUM_VIA_DIAMETER: return std::make_shared( aBase ); diff --git a/pcbnew/drc/rule_editor/panel_drc_rule_editor.cpp b/pcbnew/drc/rule_editor/panel_drc_rule_editor.cpp index faac9b5737..ab2a19796d 100644 --- a/pcbnew/drc/rule_editor/panel_drc_rule_editor.cpp +++ b/pcbnew/drc/rule_editor/panel_drc_rule_editor.cpp @@ -83,10 +83,7 @@ static bool constraintNeedsTwoObjects( DRC_RULE_EDITOR_CONSTRAINT_NAME aConstrai { switch( aConstraintType ) { - case BASIC_CLEARANCE: - case BOARD_OUTLINE_CLEARANCE: case MINIMUM_CLEARANCE: - case MINIMUM_ITEM_CLEARANCE: case CREEPAGE_DISTANCE: case COPPER_TO_HOLE_CLEARANCE: case HOLE_TO_HOLE_CLEARANCE: diff --git a/qa/tests/pcbnew/drc/test_drc_rule_editor.cpp b/qa/tests/pcbnew/drc/test_drc_rule_editor.cpp index c12ae83c8b..fe06c9f69f 100644 --- a/qa/tests/pcbnew/drc/test_drc_rule_editor.cpp +++ b/qa/tests/pcbnew/drc/test_drc_rule_editor.cpp @@ -1279,25 +1279,12 @@ BOOST_AUTO_TEST_CASE( RuleLoaderMultipleRules ) BOOST_CHECK_EQUAL( entries[0].panelType, MINIMUM_CLEARANCE ); BOOST_CHECK_EQUAL( entries[1].ruleName, "Rule B" ); - BOOST_CHECK_EQUAL( entries[1].panelType, MINIMUM_TRACK_WIDTH ); + BOOST_CHECK_EQUAL( entries[1].panelType, ROUTING_WIDTH ); BOOST_CHECK_EQUAL( entries[2].ruleName, "Rule C" ); BOOST_CHECK_EQUAL( entries[2].panelType, VIA_STYLE ); } -BOOST_AUTO_TEST_CASE( RuleLoaderRoutingWidth ) -{ - wxString ruleText = "(version 1)\n" - "(rule \"RoutingWidth\"\n" - " (constraint track_width (min 0.15mm) (opt 0.2mm) (max 0.3mm)))"; - - DRC_RULE_LOADER loader; - std::vector entries = loader.LoadFromString( ruleText ); - - BOOST_REQUIRE_EQUAL( entries.size(), 1 ); - BOOST_CHECK_EQUAL( entries[0].panelType, ROUTING_WIDTH ); -} - BOOST_AUTO_TEST_CASE( RuleLoaderEmptyRule ) { // Test: Rule with no constraints creates custom rule fallback diff --git a/resources/bitmaps_png/png/constraint_minimum_item_clearance.png b/resources/bitmaps_png/png/constraint_minimum_item_clearance.png deleted file mode 100644 index 1299a272d0..0000000000 Binary files a/resources/bitmaps_png/png/constraint_minimum_item_clearance.png and /dev/null differ diff --git a/resources/bitmaps_png/png/constraint_silk_to_silk_clearance.png b/resources/bitmaps_png/png/constraint_silk_to_silk_clearance.png index a698b54388..1299a272d0 100644 Binary files a/resources/bitmaps_png/png/constraint_silk_to_silk_clearance.png and b/resources/bitmaps_png/png/constraint_silk_to_silk_clearance.png differ diff --git a/resources/bitmaps_png/png/constraint_minimum_item_clearance_dark.png b/resources/bitmaps_png/png/constraint_silk_to_silk_clearance_dark.png similarity index 100% rename from resources/bitmaps_png/png/constraint_minimum_item_clearance_dark.png rename to resources/bitmaps_png/png/constraint_silk_to_silk_clearance_dark.png