diff --git a/pcbnew/board.cpp b/pcbnew/board.cpp
index f72e798357..93c2cddcd3 100644
--- a/pcbnew/board.cpp
+++ b/pcbnew/board.cpp
@@ -3200,3 +3200,38 @@ void BOARD::UpdateBoardOutline()
}
+int BOARD::GetPadWithPressFitAttrCount()
+{
+ // return the number of PTH with Press-Fit fabr attribute
+ int count = 0;
+
+ for( FOOTPRINT* footprint : Footprints() )
+ {
+ for( PAD* pad : footprint->Pads() )
+ {
+ if( pad->GetProperty() == PAD_PROP::PRESSFIT )
+ count++;
+ }
+ }
+
+ return count;
+}
+
+
+int BOARD::GetPadWithCastellatedAttrCount()
+{
+ // @return the number of PTH with Castellated fabr attribute
+ int count = 0;
+
+ for( FOOTPRINT* footprint : Footprints() )
+ {
+ for( PAD* pad : footprint->Pads() )
+ {
+ if( pad->GetProperty() == PAD_PROP::CASTELLATED )
+ count++;
+ }
+ }
+
+ return count;
+}
+
diff --git a/pcbnew/board.h b/pcbnew/board.h
index 2ac10df4d1..a43cf6aec3 100644
--- a/pcbnew/board.h
+++ b/pcbnew/board.h
@@ -967,6 +967,16 @@ public:
return m_NetInfo.GetNetCount();
}
+ /**
+ * @return the number of PTH with Press-Fit fabr attribute
+ */
+ int GetPadWithPressFitAttrCount();
+
+ /**
+ * @return the number of PTH with Castellated fabr attribute
+ */
+ int GetPadWithCastellatedAttrCount();
+
/**
* Calculate the bounding box containing all board items (or board edge segments).
*
diff --git a/pcbnew/board_stackup_manager/board_stackup.cpp b/pcbnew/board_stackup_manager/board_stackup.cpp
index 56b55722ff..f5f487916f 100644
--- a/pcbnew/board_stackup_manager/board_stackup.cpp
+++ b/pcbnew/board_stackup_manager/board_stackup.cpp
@@ -353,7 +353,6 @@ BOARD_STACKUP::BOARD_STACKUP()
// (Loss tg and Epison R)
m_HasThicknessConstrains = false; // True if some dielectric or copper layers have constrains
m_EdgeConnectorConstraints = BS_EDGE_CONNECTOR_NONE;
- m_CastellatedPads = false; // True if some castellated pads exist
m_EdgePlating = false; // True if edge board is plated
m_FinishType = wxT( "None" ); // undefined finish type
}
@@ -364,7 +363,6 @@ BOARD_STACKUP::BOARD_STACKUP( const BOARD_STACKUP& aOther )
m_HasDielectricConstrains = aOther.m_HasDielectricConstrains;
m_HasThicknessConstrains = aOther.m_HasThicknessConstrains;
m_EdgeConnectorConstraints = aOther.m_EdgeConnectorConstraints;
- m_CastellatedPads = aOther.m_CastellatedPads;
m_EdgePlating = aOther.m_EdgePlating;
m_FinishType = aOther.m_FinishType;
@@ -383,7 +381,6 @@ BOARD_STACKUP& BOARD_STACKUP::operator=( const BOARD_STACKUP& aOther )
m_HasDielectricConstrains = aOther.m_HasDielectricConstrains;
m_HasThicknessConstrains = aOther.m_HasThicknessConstrains;
m_EdgeConnectorConstraints = aOther.m_EdgeConnectorConstraints;
- m_CastellatedPads = aOther.m_CastellatedPads;
m_EdgePlating = aOther.m_EdgePlating;
m_FinishType = aOther.m_FinishType;
@@ -406,7 +403,6 @@ bool BOARD_STACKUP::operator==( const BOARD_STACKUP& aOther ) const
if( m_HasDielectricConstrains != aOther.m_HasDielectricConstrains ) return false;
if( m_HasThicknessConstrains != aOther.m_HasThicknessConstrains ) return false;
if( m_EdgeConnectorConstraints != aOther.m_EdgeConnectorConstraints ) return false;
- if( m_CastellatedPads != aOther.m_CastellatedPads ) return false;
if( m_EdgePlating != aOther.m_EdgePlating ) return false;
if( m_FinishType != aOther.m_FinishType ) return false;
@@ -606,7 +602,6 @@ bool BOARD_STACKUP::SynchronizeWithBoard( BOARD_DESIGN_SETTINGS* aSettings )
const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
m_HasDielectricConstrains = source_stackup.m_HasDielectricConstrains;
m_EdgeConnectorConstraints = source_stackup.m_EdgeConnectorConstraints;
- m_CastellatedPads = source_stackup.m_CastellatedPads;
m_EdgePlating = source_stackup.m_EdgePlating;
m_FinishType = source_stackup.m_FinishType;
@@ -732,7 +727,6 @@ void BOARD_STACKUP::BuildDefaultStackupList( const BOARD_DESIGN_SETTINGS* aSetti
const BOARD_STACKUP& source_stackup = aSettings->GetStackupDescriptor();
m_EdgeConnectorConstraints = source_stackup.m_EdgeConnectorConstraints;
m_HasDielectricConstrains = source_stackup.m_HasDielectricConstrains;
- m_CastellatedPads = source_stackup.m_CastellatedPads;
m_EdgePlating = source_stackup.m_EdgePlating;
m_FinishType = source_stackup.m_FinishType;
}
@@ -817,9 +811,6 @@ void BOARD_STACKUP::FormatBoardStackup( OUTPUTFORMATTER* aFormatter, const BOARD
m_EdgeConnectorConstraints > 1 ? "bevelled": "yes" );
}
- if( m_CastellatedPads )
- KICAD_FORMAT::FormatBool( aFormatter, "castellated_pads", true );
-
if( m_EdgePlating )
KICAD_FORMAT::FormatBool( aFormatter, "edge_plating", true );
diff --git a/pcbnew/board_stackup_manager/board_stackup.h b/pcbnew/board_stackup_manager/board_stackup.h
index a9d53c9a95..e46663def6 100644
--- a/pcbnew/board_stackup_manager/board_stackup.h
+++ b/pcbnew/board_stackup_manager/board_stackup.h
@@ -330,7 +330,6 @@ public:
*/
BS_EDGE_CONNECTOR_CONSTRAINTS m_EdgeConnectorConstraints;
- bool m_CastellatedPads; ///< True if castellated pads exist
bool m_EdgePlating; ///< True if the edge board is plated
private:
diff --git a/pcbnew/board_stackup_manager/board_stackup_reporter.cpp b/pcbnew/board_stackup_manager/board_stackup_reporter.cpp
index dd80f14a1b..4e48fcd92f 100644
--- a/pcbnew/board_stackup_manager/board_stackup_reporter.cpp
+++ b/pcbnew/board_stackup_manager/board_stackup_reporter.cpp
@@ -133,9 +133,6 @@ wxString BuildStackupReport( BOARD_STACKUP& aStackup, EDA_UNITS aUnits )
if( aStackup.m_EdgePlating )
report << wxT( " Option \"Plated edges\"" );
- if( aStackup.m_CastellatedPads )
- report << wxT( " Option \"Castellated Pads\"" );
-
if( aStackup.m_EdgeConnectorConstraints != BS_EDGE_CONNECTOR_NONE )
{
wxString conn_txt = wxT( "yes" );
diff --git a/pcbnew/board_stackup_manager/panel_board_finish.cpp b/pcbnew/board_stackup_manager/panel_board_finish.cpp
index de72013749..84ceee9182 100644
--- a/pcbnew/board_stackup_manager/panel_board_finish.cpp
+++ b/pcbnew/board_stackup_manager/panel_board_finish.cpp
@@ -55,7 +55,6 @@ void PANEL_SETUP_BOARD_FINISH::synchronizeWithBoard()
const BOARD_STACKUP& brd_stackup = m_brdSettings->GetStackupDescriptor();
m_choiceEdgeConn->SetSelection( brd_stackup.m_EdgeConnectorConstraints );
- m_cbCastellatedPads->SetValue( brd_stackup.m_CastellatedPads );
m_cbEgdesPlated->SetValue( brd_stackup.m_EdgePlating );
// find the choice depending on the initial finish setting
@@ -98,9 +97,6 @@ bool PANEL_SETUP_BOARD_FINISH::TransferDataFromWindow( BOARD_STACKUP& aStackup )
modified |= aStackup.m_EdgeConnectorConstraints != (BS_EDGE_CONNECTOR_CONSTRAINTS) edge;
aStackup.m_EdgeConnectorConstraints = (BS_EDGE_CONNECTOR_CONSTRAINTS) edge;
- modified |= aStackup.m_CastellatedPads != m_cbCastellatedPads->GetValue();
- aStackup.m_CastellatedPads = m_cbCastellatedPads->GetValue();
-
modified |= aStackup.m_EdgePlating != m_cbEgdesPlated->GetValue();
aStackup.m_EdgePlating = m_cbEgdesPlated->GetValue();
diff --git a/pcbnew/board_stackup_manager/panel_board_finish_base.cpp b/pcbnew/board_stackup_manager/panel_board_finish_base.cpp
index 89a4eab655..d6b757e61b 100644
--- a/pcbnew/board_stackup_manager/panel_board_finish_base.cpp
+++ b/pcbnew/board_stackup_manager/panel_board_finish_base.cpp
@@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////////
-// C++ code generated with wxFormBuilder (version Oct 26 2018)
+// C++ code generated with wxFormBuilder (version 4.2.1-0-g80c4cb6)
// http://www.wxformbuilder.org/
//
// PLEASE DO *NOT* EDIT THIS FILE!
@@ -17,9 +17,6 @@ PANEL_SETUP_BOARD_FINISH_BASE::PANEL_SETUP_BOARD_FINISH_BASE( wxWindow* parent,
wxBoxSizer* bMargins;
bMargins = new wxBoxSizer( wxVERTICAL );
- m_cbCastellatedPads = new wxCheckBox( this, wxID_ANY, _("Has castellated pads"), wxDefaultPosition, wxDefaultSize, 0 );
- bMargins->Add( m_cbCastellatedPads, 0, wxTOP|wxBOTTOM|wxLEFT, 5 );
-
m_cbEgdesPlated = new wxCheckBox( this, wxID_ANY, _("Plated board edge"), wxDefaultPosition, wxDefaultSize, 0 );
bMargins->Add( m_cbEgdesPlated, 0, wxBOTTOM|wxLEFT, 5 );
diff --git a/pcbnew/board_stackup_manager/panel_board_finish_base.fbp b/pcbnew/board_stackup_manager/panel_board_finish_base.fbp
index 5eae5a676a..a42979a046 100644
--- a/pcbnew/board_stackup_manager/panel_board_finish_base.fbp
+++ b/pcbnew/board_stackup_manager/panel_board_finish_base.fbp
@@ -1,467 +1,414 @@
-
+
-
-
diff --git a/pcbnew/board_stackup_manager/panel_board_finish_base.h b/pcbnew/board_stackup_manager/panel_board_finish_base.h
index 26809f6e32..c3995c2bce 100644
--- a/pcbnew/board_stackup_manager/panel_board_finish_base.h
+++ b/pcbnew/board_stackup_manager/panel_board_finish_base.h
@@ -1,5 +1,5 @@
///////////////////////////////////////////////////////////////////////////
-// C++ code generated with wxFormBuilder (version Oct 26 2018)
+// C++ code generated with wxFormBuilder (version 4.2.1-0-g80c4cb6)
// http://www.wxformbuilder.org/
//
// PLEASE DO *NOT* EDIT THIS FILE!
@@ -23,7 +23,6 @@
///////////////////////////////////////////////////////////////////////////
-
///////////////////////////////////////////////////////////////////////////////
/// Class PANEL_SETUP_BOARD_FINISH_BASE
///////////////////////////////////////////////////////////////////////////////
@@ -32,7 +31,6 @@ class PANEL_SETUP_BOARD_FINISH_BASE : public wxPanel
private:
protected:
- wxCheckBox* m_cbCastellatedPads;
wxCheckBox* m_cbEgdesPlated;
wxStaticText* m_staticTextFinish;
wxChoice* m_choiceFinish;
@@ -42,6 +40,7 @@ class PANEL_SETUP_BOARD_FINISH_BASE : public wxPanel
public:
PANEL_SETUP_BOARD_FINISH_BASE( wxWindow* parent, wxWindowID id = wxID_ANY, const wxPoint& pos = wxDefaultPosition, const wxSize& size = wxSize( -1,-1 ), long style = wxTAB_TRAVERSAL, const wxString& name = wxEmptyString );
+
~PANEL_SETUP_BOARD_FINISH_BASE();
};
diff --git a/pcbnew/dialogs/dialog_pad_properties_base.cpp b/pcbnew/dialogs/dialog_pad_properties_base.cpp
index 2f9724dea9..add12457ab 100644
--- a/pcbnew/dialogs/dialog_pad_properties_base.cpp
+++ b/pcbnew/dialogs/dialog_pad_properties_base.cpp
@@ -613,7 +613,7 @@ DIALOG_PAD_PROPERTIES_BASE::DIALOG_PAD_PROPERTIES_BASE( wxWindow* parent, wxWind
m_middleBoxSizer->Add( 0, 2, 0, wxEXPAND, 5 );
- wxString m_choiceFabPropertyChoices[] = { _("None"), _("BGA pad"), _("Fiducial, local to footprint"), _("Fiducial, global to board"), _("Test point pad"), _("Heatsink pad"), _("Castellated pad (through hole only)"), _("Mechanical"), _("Press-fit (through hole only)") };
+ wxString m_choiceFabPropertyChoices[] = { _("None"), _("BGA pad"), _("Fiducial, local to footprint"), _("Fiducial, global to board"), _("Test point pad"), _("Heatsink pad"), _("Castellated pad (through hole only)"), _("Mechanical"), _("Press-fit (round through hole only)") };
int m_choiceFabPropertyNChoices = sizeof( m_choiceFabPropertyChoices ) / sizeof( wxString );
m_choiceFabProperty = new wxChoice( m_panelGeneral, wxID_ANY, wxDefaultPosition, wxDefaultSize, m_choiceFabPropertyNChoices, m_choiceFabPropertyChoices, 0 );
m_choiceFabProperty->SetSelection( 0 );
diff --git a/pcbnew/dialogs/dialog_pad_properties_base.fbp b/pcbnew/dialogs/dialog_pad_properties_base.fbp
index 1bffcb03bf..5cf239380b 100644
--- a/pcbnew/dialogs/dialog_pad_properties_base.fbp
+++ b/pcbnew/dialogs/dialog_pad_properties_base.fbp
@@ -7477,7 +7477,7 @@
1
0
- "None" "BGA pad" "Fiducial, local to footprint" "Fiducial, global to board" "Test point pad" "Heatsink pad" "Castellated pad (through hole only)" "Mechanical" "Press-fit (through hole only)"
+ "None" "BGA pad" "Fiducial, local to footprint" "Fiducial, global to board" "Test point pad" "Heatsink pad" "Castellated pad (through hole only)" "Mechanical" "Press-fit (round through hole only)"
1
1
diff --git a/pcbnew/exporters/gerber_jobfile_writer.cpp b/pcbnew/exporters/gerber_jobfile_writer.cpp
index 75efb8efd1..a1525167ba 100644
--- a/pcbnew/exporters/gerber_jobfile_writer.cpp
+++ b/pcbnew/exporters/gerber_jobfile_writer.cpp
@@ -268,8 +268,15 @@ void GERBER_JOBFILE_WRITER::addJSONGeneralSpecs()
if( brd_stackup.m_HasDielectricConstrains )
m_json["GeneralSpecs"]["ImpedanceControlled"] = true;
+ #if 0 // Old way to set property
if( brd_stackup.m_CastellatedPads )
m_json["GeneralSpecs"]["Castellated"] = true;
+ #endif
+ if( m_pcb->GetPadWithCastellatedAttrCount() )
+ m_json["GeneralSpecs"]["Castellated"] = true;
+
+ if( m_pcb->GetPadWithPressFitAttrCount() )
+ m_json["GeneralSpecs"]["Press-fit"] = true;
if( brd_stackup.m_EdgePlating )
m_json["GeneralSpecs"]["EdgePlating"] = true;
diff --git a/pcbnew/footprint.cpp b/pcbnew/footprint.cpp
index 429fcbcbae..bf5d37ddcd 100644
--- a/pcbnew/footprint.cpp
+++ b/pcbnew/footprint.cpp
@@ -1263,6 +1263,7 @@ int FOOTPRINT::GetLikelyAttribute() const
case PAD_PROP::NONE:
case PAD_PROP::BGA:
case PAD_PROP::TESTPOINT:
+ case PAD_PROP::PRESSFIT:
break;
}
diff --git a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
index 35d3daa039..c8c0655e66 100644
--- a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
+++ b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr.h
@@ -184,7 +184,8 @@ class PCB_IO_KICAD_SEXPR; // forward decl
//#define SEXPR_BOARD_FILE_VERSION 20250324 // Jumper pads
//#define SEXPR_BOARD_FILE_VERSION 20250401 // Time domain length tuning
//#define SEXPR_BOARD_FILE_VERSION 20250513 // Groups can have design block lib_id
-#define SEXPR_BOARD_FILE_VERSION 20250801 // (island) -> (island yes/no)
+//#define SEXPR_BOARD_FILE_VERSION 20250801 // (island) -> (island yes/no)
+#define SEXPR_BOARD_FILE_VERSION 20250811 // press-fit pad fabr prop support
#define BOARD_FILE_HOST_VERSION 20200825 ///< Earlier files than this include the host tag
#define LEGACY_ARC_FORMATTING 20210925 ///< These were the last to use old arc formatting
diff --git a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
index 145bc0adf1..7ef4b24a0c 100644
--- a/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
+++ b/pcbnew/pcb_io/kicad_sexpr/pcb_io_kicad_sexpr_parser.cpp
@@ -1688,16 +1688,16 @@ void PCB_IO_KICAD_SEXPR_PARSER::parseBoardStackup()
NeedRIGHT();
break;
- case T_castellated_pads:
+ case T_castellated_pads: // Legacy compatibility. just skip it
token = NextTok();
- stackup.m_CastellatedPads = token == T_yes;
NeedRIGHT();
break;
default:
// Currently, skip this item if not defined, because the stackup def
// is a moving target
- //Expecting( "copper_finish, edge_plating, dielectric_constrains, edge_connector, castellated_pads" );
+ //Expecting( "copper_finish, edge_plating, dielectric_constrains,
+ // edge_connector, castellated_pads" );
skipCurrent();
break;
}
diff --git a/pcbnew/tools/pcb_control.cpp b/pcbnew/tools/pcb_control.cpp
index 014044e0da..8e96df1eac 100644
--- a/pcbnew/tools/pcb_control.cpp
+++ b/pcbnew/tools/pcb_control.cpp
@@ -2386,7 +2386,12 @@ int PCB_CONTROL::PlaceCharacteristics( const TOOL_EVENT& aEvent )
addDataCell( stackup.m_HasDielectricConstrains ? _( "Yes" ) : _( "No" ) );
addDataCell( _( "Castellated pads: " ) );
- addDataCell( stackup.m_CastellatedPads ? _( "Yes" ) : _( "No" ) );
+ int castellated_pad_count = m_frame->GetBoard()->GetPadWithCastellatedAttrCount();
+ addDataCell( castellated_pad_count ? _( "Yes" ) : _( "No" ) );
+
+ addDataCell( _( "Press-fit pads: " ) );
+ int pressfit_pad_count = m_frame->GetBoard()->GetPadWithPressFitAttrCount();
+ addDataCell( pressfit_pad_count ? _( "Yes" ) : _( "No" ) );
addDataCell( _( "Plated board edge: " ) );
addDataCell( stackup.m_EdgePlating ? _( "Yes" ) : _( "No" ) );
@@ -2403,8 +2408,14 @@ int PCB_CONTROL::PlaceCharacteristics( const TOOL_EVENT& aEvent )
addDataCell( _( "Edge card connectors: " ) );
addDataCell( msg );
- addDataCell( wxEmptyString );
- addDataCell( wxEmptyString );
+ // We are building a table having 4 columns.
+ // So we must have a cell count multible of 4, to have fully build row.
+ // Othewise the table is really badly drawn.
+ std::vector cells_list = table->GetCells();
+ int cell_to_add_cnt = cells_list.size() % table->GetColCount();
+
+ for( int ii = 0; ii < cell_to_add_cnt; ii++ )
+ addDataCell( wxEmptyString );
table->SetStrokeExternal( false );
table->SetStrokeHeaderSeparator( false );