From 07d6cbaeb70321338fbc7c3ccc6b400a5ba2ce0b Mon Sep 17 00:00:00 2001 From: jean-pierre charras Date: Thu, 18 Jun 2015 15:19:30 +0200 Subject: [PATCH] Vias, creation and editon: fix a bug in legacy mode when creating a micro-via (the drill diameter was the standard vias drill, not the micro-via drill). Also in global vas edition, always set the via drill to the actual current netclass value (do not use anymore the 0 value as default), to avoid unwanted invisible drill change for existing vias when the netclass value is modified. This is consistent with the via creation, in GAL mode --- pcbnew/class_track.cpp | 44 ++++++++++++++++++++++++++++++--- pcbnew/drc_marker_functions.cpp | 2 +- pcbnew/edit_track_width.cpp | 25 +++++++++++++++---- pcbnew/editrack-part2.cpp | 24 +++++++++--------- 4 files changed, 74 insertions(+), 21 deletions(-) diff --git a/pcbnew/class_track.cpp b/pcbnew/class_track.cpp index 395e679428..0d0723b41d 100644 --- a/pcbnew/class_track.cpp +++ b/pcbnew/class_track.cpp @@ -837,8 +837,24 @@ void VIA::Draw( EDA_DRAW_PANEL* panel, wxDC* aDC, GR_DRAWMODE aDrawMode, const w if( displ_opts->m_DisplayViaMode != VIA_HOLE_NOT_SHOW ) { // Display all drill holes requested or Display non default holes requested - if( (displ_opts->m_DisplayViaMode == ALL_VIA_HOLE_SHOW) - || ( (drill_radius > 0 ) && !IsDrillDefault() ) ) + bool show_hole = displ_opts->m_DisplayViaMode == ALL_VIA_HOLE_SHOW; + + if( !show_hole ) + { + NETINFO_ITEM* net = GetNet(); + int drill_class_value = 0; + if( net ) + { + if( GetViaType() == VIA_MICROVIA ) + drill_class_value = net->GetMicroViaDrillSize(); + else + drill_class_value = net->GetViaDrillSize(); + } + + show_hole = GetDrillValue() != drill_class_value; + } + + if( show_hole ) { if( fillvia ) { @@ -1208,6 +1224,7 @@ void VIA::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) LAYER_ID top_layer, bottom_layer; LayerPair( &top_layer, &bottom_layer ); + if( board ) msg = board->GetLayerName( top_layer ) + wxT( "/" ) + board->GetLayerName( bottom_layer ); @@ -1230,10 +1247,29 @@ void VIA::GetMsgPanelInfoBase( std::vector< MSG_PANEL_ITEM >& aList ) wxString title = _( "Drill" ); title += wxT( " " ); - if( m_Drill >= 0 ) + bool drl_specific = true; + + if( GetBoard() ) + { + NETINFO_ITEM* net = GetNet(); + int drill_class_value = 0; + + if( net ) + { + if( GetViaType() == VIA_MICROVIA ) + drill_class_value = net->GetMicroViaDrillSize(); + else + drill_class_value = net->GetViaDrillSize(); + } + + drl_specific = drill_value != drill_class_value; + } + + + if( drl_specific ) title += _( "(Specific)" ); else - title += _( "(Default)" ); + title += _( "(NetClass)" ); aList.push_back( MSG_PANEL_ITEM( title, msg, RED ) ); } diff --git a/pcbnew/drc_marker_functions.cpp b/pcbnew/drc_marker_functions.cpp index 0bf1ab689b..56423612fa 100644 --- a/pcbnew/drc_marker_functions.cpp +++ b/pcbnew/drc_marker_functions.cpp @@ -29,7 +29,7 @@ /* Methods of class DRC to initialize drc markers with messages - * according to items and error ode + * according to items and error code */ #include diff --git a/pcbnew/edit_track_width.cpp b/pcbnew/edit_track_width.cpp index 4ffd73c7f5..0a6560e8ed 100644 --- a/pcbnew/edit_track_width.cpp +++ b/pcbnew/edit_track_width.cpp @@ -73,12 +73,14 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, { const VIA *via = static_cast( aTrackItem ); - if( !via->IsDrillDefault() ) - initial_drill = via->GetDrillValue(); + // Get the draill value, regardless it is default or specific + initial_drill = via->GetDrillValue(); if( net ) { new_width = net->GetViaSize(); + new_drill = GetDesignSettings().GetCurrentViaDrill(); + new_drill = net->GetViaDrillSize(); } else { @@ -89,10 +91,22 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, if( via->GetViaType() == VIA_MICROVIA ) { if( net ) + { new_width = net->GetMicroViaSize(); + new_drill = net->GetMicroViaDrillSize(); + } else new_width = GetDesignSettings().GetCurrentMicroViaSize(); } + + // Old versions set a drill value <= 0, when the default netclass it used + // but it could be better to set the drill value to the actual value + // to avoid issues for existing vias, if the default drill value is modified + // in the netclass, and not in current vias. + if( via->GetDrill() <= 0 ) // means default netclass drill value used + { + initial_drill = -1; // Force drill vias re-initialization + } } aTrackItem->SetWidth( new_width ); @@ -112,10 +126,11 @@ bool PCB_EDIT_FRAME::SetTrackSegmentWidth( TRACK* aTrackItem, { change_ok = true; } - else if( (aTrackItem->Type() == PCB_VIA_T) && (initial_drill != new_drill) ) + else if( (aTrackItem->Type() == PCB_VIA_T) ) { - // if new width == initial_width: do nothing, unless a via has its drill value changed - change_ok = true; + // if a via has its drill value changed, force change + if( initial_drill != new_drill ) + change_ok = true; } if( change_ok ) diff --git a/pcbnew/editrack-part2.cpp b/pcbnew/editrack-part2.cpp index 32409a4893..c84d9ddc4c 100644 --- a/pcbnew/editrack-part2.cpp +++ b/pcbnew/editrack-part2.cpp @@ -1,10 +1,10 @@ /* * This program source code file is part of KiCad, a free EDA CAD application. * - * Copyright (C) 2012 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr + * Copyright (C) 2015 Jean-Pierre Charras, jean-pierre.charras@ujf-grenoble.fr * Copyright (C) 2012 SoftPLC Corporation, Dick Hollenbeck * Copyright (C) 2012 Wayne Stambaugh - * Copyright (C) 1992-2012 KiCad Developers, see AUTHORS.txt for contributors. + * Copyright (C) 1992-2015 KiCad Developers, see AUTHORS.txt for contributors. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License @@ -97,15 +97,16 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC ) VIA* via = new VIA( GetBoard() ); via->SetFlags( IS_NEW ); via->SetViaType( GetDesignSettings().m_CurrentViaType ); - via->SetWidth( GetDesignSettings().GetCurrentViaSize()); via->SetNetCode( GetBoard()->GetHighLightNetCode() ); - via->SetEnd( g_CurrentTrackSegment->GetEnd() ); - via->SetStart( g_CurrentTrackSegment->GetEnd() ); + via->SetPosition( g_CurrentTrackSegment->GetEnd() ); + + // for microvias, the size and hole will be changed later. + via->SetWidth( GetDesignSettings().GetCurrentViaSize()); + via->SetDrill( GetDesignSettings().GetCurrentViaDrill() ); // Usual via is from copper to component. // layer pair is B_Cu and F_Cu. via->SetLayerPair( B_Cu, F_Cu ); - via->SetDrill( GetDesignSettings().GetCurrentViaDrill() ); LAYER_ID first_layer = GetActiveLayer(); LAYER_ID last_layer; @@ -135,13 +136,14 @@ bool PCB_EDIT_FRAME::Other_Layer_Route( TRACK* aTrack, wxDC* DC ) last_layer = B_Cu; else if( first_layer == In1_Cu ) last_layer = F_Cu; - // else error: will be removed later via->SetLayerPair( first_layer, last_layer ); - { - NETINFO_ITEM* net = via->GetNet(); - via->SetWidth( net->GetMicroViaSize() ); - } + + // Update diameter and hole size, which where set previously + // for normal vias + NETINFO_ITEM* net = via->GetNet(); + via->SetWidth( net->GetMicroViaSize() ); + via->SetDrill( net->GetMicroViaDrillSize() ); } break;