clement
287 lines
15 KiB
C
287 lines
15 KiB
C
/*
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* es8388.c — ES8388 codec driver (IDF 5.x, legacy I2C driver API).
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*
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* Register map reference: ES8388 datasheet rev 1.6 (Everest Semiconductor).
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* Init sequence derived from:
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* - Espressif esp-adf es8388.c (Apache 2.0)
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* - schreibfaul1/ESP32-audioI2S ES8388 init (MIT)
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* - AI-Thinker SDK AudioKit driver
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*
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* The sequence configures the ES8388 for:
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* - Master clock: MCLK from ESP32 GPIO0 at 12.288 MHz (or 256*Fs at 16kHz)
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* - I2S format: I2S Philips, 16-bit, stereo
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* - DAC: LOUT1/ROUT1 → headphone amp (GPIO21 PA_ENABLE must be HIGH)
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* - ADC: LINPUT1/RINPUT1 mic (differential), gain 24 dB
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* - Sample rate: 16 kHz (MCLKDIV = 256Fs)
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*/
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#include "es8388.h"
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#include "board_config.h"
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#include <string.h>
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#include "driver/i2c.h"
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#include "driver/gpio.h"
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#include "esp_log.h"
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#define TAG "es8388"
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/* ── ES8388 register addresses ──────────────────────────────────────────── */
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#define ES8388_CHIP_CTL1 0x00 /* CHIP_CTL1 */
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#define ES8388_CHIP_CTL2 0x01 /* CHIP_CTL2 */
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#define ES8388_CHIP_POWER 0x02 /* CHIP_POWER (ADCPD, DACPD, etc.) */
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#define ES8388_ADC_POWER 0x03 /* ADCPOWER */
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#define ES8388_DAC_POWER 0x04 /* DACPOWER */
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#define ES8388_CHIP_LP 0x05 /* CHIP_LP */
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#define ES8388_CHIP_CTL3 0x06 /* CHIP_CTL3 */
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#define ES8388_ADC_CTL1 0x09 /* ADCCONTROL1 — PGA gain */
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#define ES8388_ADC_CTL2 0x0A /* ADCCONTROL2 — input select (LINSEL/RINSEL) */
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#define ES8388_ADC_CTL3 0x0B /* ADCCONTROL3 — DS/DS filter select */
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#define ES8388_ADC_CTL4 0x0C /* ADCCONTROL4 — I2S format / word length */
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#define ES8388_ADC_CTL5 0x0D /* ADCCONTROL5 — MCLK divider (RATIO=256) */
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#define ES8388_ADC_CTL7 0x0F /* ADCCONTROL7 — HPF enable/config */
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#define ES8388_ADC_CTL8 0x10 /* ADCCONTROL8 — ADC L volume */
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#define ES8388_ADC_CTL9 0x11 /* ADCCONTROL9 — ADC R volume */
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#define ES8388_DAC_CTL1 0x17 /* DACCONTROL1 — I2S word len / format */
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#define ES8388_DAC_CTL2 0x18 /* DACCONTROL2 — MCLK divider */
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#define ES8388_DAC_CTL3 0x19 /* DACCONTROL3 — mute */
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#define ES8388_DAC_CTL4 0x1A /* DACCONTROL4 — LDACVOL */
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#define ES8388_DAC_CTL5 0x1B /* DACCONTROL5 — RDACVOL */
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#define ES8388_DAC_CTL16 0x26 /* DACCONTROL16 — L/R mixer config */
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#define ES8388_DAC_CTL17 0x27 /* DACCONTROL17 — L mixer gain */
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#define ES8388_DAC_CTL20 0x2A /* DACCONTROL20 — R mixer gain */
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#define ES8388_DAC_CTL21 0x2B /* DACCONTROL21 — ADC/DAC LRCK sync (bit7=1 for full-duplex) */
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#define ES8388_DAC_CTL22 0x2C /* DACCONTROL22 — (unused in this config) */
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#define ES8388_DAC_CTL23 0x2D /* DACCONTROL23 — (unused in this config) */
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#define ES8388_DAC_CTL24 0x2E /* DACCONTROL24 — LOUT1VOL (OUT1 left volume) */
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#define ES8388_DAC_CTL25 0x2F /* DACCONTROL25 — ROUT1VOL (OUT1 right volume) */
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#define ES8388_DAC_CTL26 0x30 /* DACCONTROL26 — LOUT2VOL (OUT2 left volume) */
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/* Volume register: 0x00=0dB (max), 0x21=-33dB step per 1.5dB, 0x24=mute. */
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#define ES8388_VOL_MAX 0x00
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#define ES8388_VOL_0DB 0x00
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#define ES8388_VOL_MUTE 0x24
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/* ── I2C helpers ─────────────────────────────────────────────────────────── */
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static esp_err_t i2c_write_reg(uint8_t reg, uint8_t value)
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{
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uint8_t buf[2] = { reg, value };
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esp_err_t ret = i2c_master_write_to_device(PLIP_I2C_PORT,
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PLIP_ES8388_ADDR,
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buf, sizeof(buf),
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pdMS_TO_TICKS(100));
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "write reg 0x%02X=0x%02X failed: %s",
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reg, value, esp_err_to_name(ret));
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}
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return ret;
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}
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esp_err_t es8388_read_reg(uint8_t reg, uint8_t *value)
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{
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return i2c_master_write_read_device(PLIP_I2C_PORT,
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PLIP_ES8388_ADDR,
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®, 1,
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value, 1,
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pdMS_TO_TICKS(100));
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}
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esp_err_t es8388_write_reg(uint8_t reg, uint8_t value)
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{
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return i2c_write_reg(reg, value);
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}
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/* ── Public API ──────────────────────────────────────────────────────────── */
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esp_err_t es8388_init(void)
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{
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/* Initialise I2C master on the A1S bus. */
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i2c_config_t conf = {
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.mode = I2C_MODE_MASTER,
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.sda_io_num = PLIP_I2C_SDA,
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.scl_io_num = PLIP_I2C_SCL,
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.sda_pullup_en = GPIO_PULLUP_ENABLE,
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.scl_pullup_en = GPIO_PULLUP_ENABLE,
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.master.clk_speed = PLIP_I2C_FREQ_HZ,
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};
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esp_err_t ret = i2c_param_config(PLIP_I2C_PORT, &conf);
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if (ret != ESP_OK) return ret;
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ret = i2c_driver_install(PLIP_I2C_PORT, conf.mode, 0, 0, 0);
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if (ret != ESP_OK && ret != ESP_ERR_INVALID_STATE) {
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/* ESP_ERR_INVALID_STATE means the driver is already installed — ok. */
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ESP_LOGE(TAG, "i2c_driver_install: %s", esp_err_to_name(ret));
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return ret;
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}
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/* Quick device presence check. */
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uint8_t chip_id = 0;
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ret = es8388_read_reg(ES8388_CHIP_CTL1, &chip_id);
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if (ret != ESP_OK) {
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ESP_LOGE(TAG, "ES8388 not found on I2C bus (addr=0x%02X): %s",
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PLIP_ES8388_ADDR, esp_err_to_name(ret));
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return ret;
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}
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ESP_LOGI(TAG, "ES8388 detected: CHIP_CTL1=0x%02X", chip_id);
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/* ── Full power-up + init sequence ─────────────────────────────────── */
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/* 1. Reset. */
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if (i2c_write_reg(ES8388_CHIP_CTL1, 0x80) != ESP_OK) return ESP_FAIL;
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vTaskDelay(pdMS_TO_TICKS(20));
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if (i2c_write_reg(ES8388_CHIP_CTL1, 0x00) != ESP_OK) return ESP_FAIL;
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/* 2. Power down all blocks first (prevents pop on line-up). */
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if (i2c_write_reg(ES8388_CHIP_POWER, 0xFF) != ESP_OK) return ESP_FAIL;
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/* 3. CONTROL1: WORK_MODE = record+playback (0x10), VMIDSEL=10 (0x02).
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* 0x12 = 0b00010010 — enables both ADC and DAC paths.
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* Previous value 0x05 only enabled playback (WORK_MODE=00). */
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if (i2c_write_reg(ES8388_CHIP_CTL1, 0x12) != ESP_OK) return ESP_FAIL;
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/* 3b. CONTROL2 (0x01): VROI=0, LPVrefBuf=0, normal operation. */
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if (i2c_write_reg(ES8388_CHIP_CTL2, 0x50) != ESP_OK) return ESP_FAIL;
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/* 3c. Internal DLL stabilisation for LOW sample rates (16 kHz). UNDOCUMENTED
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* registers 0x35/0x37/0x39 — the proven A252 driver (hardware/projects/
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* slic-phone Es8388Driver.cpp) sets these to "disable internal DLL for low
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* sample-rate stability". WITHOUT them the ADC clock domain is unstable at
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* 16 kHz and the ADC outputs a frozen DC value (capture = flat, no AC) even
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* though analog signal is present on the LIN pin — exactly our symptom. The
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* DAC tolerates it, which is why playback worked but capture didn't. They
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* must be set here in the boot sequence (a live poke can't re-lock the DLL). */
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if (i2c_write_reg(0x35, 0xA0) != ESP_OK) return ESP_FAIL;
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if (i2c_write_reg(0x37, 0xD0) != ESP_OK) return ESP_FAIL;
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if (i2c_write_reg(0x39, 0xD0) != ESP_OK) return ESP_FAIL;
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/* 4. Clock: MCLK divider = 256*Fs, DAC SRC = MCLK. */
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if (i2c_write_reg(0x08, 0x00) != ESP_OK) return ESP_FAIL; /* MASTERMODE = slave */
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/* 5. ADC power: power down to allow clean register writes. */
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if (i2c_write_reg(ES8388_ADC_POWER, 0xFF) != ESP_OK) return ESP_FAIL;
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/* 6. ADC config (follows Espressif esp-codec-dev reference sequence):
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* - ADCCONTROL1 (0x09) = 0xBB: MIC PGA +24dB L and R
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* - ADCCONTROL2 (0x0A) = 0x50: LINSEL=10 LIN2/RIN2 (telephone handset mic)
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* Value 0x00 = LIN1 differential, 0x50 = LIN2 single-ended (A1S combiné)
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* - ADCCONTROL3 (0x0B) = 0x02: DS filter select (required by reference)
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* - ADCCONTROL4 (0x0C) = 0x0C: I2S Philips 16-bit word length
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* - ADCCONTROL5 (0x0D) = 0x02: ADCFsMode SINGLE SPEED RATIO=256 (16kHz@MCLK 4.096MHz)
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* - ADCCONTROL8/9 (0x10/0x11) = 0x00: ADC digital volume 0dB */
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if (i2c_write_reg(ES8388_ADC_CTL1, 0x44) != ESP_OK) return ESP_FAIL; /* MIC PGA +12dB L+R (was +24dB: too hot for a close handset mic → clipping/feedback) */
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/* ADCCONTROL2 (0x0A): input select. The K50835F SLIC handset transmit audio is
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* wired to LIN2/RIN2 on this bench — PROVEN: speech captured (ACrms 196, crest 10.3)
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* on 0x50, vs DC-only floating offset on 0x00 (LIN1). */
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if (i2c_write_reg(ES8388_ADC_CTL2, 0x50) != ESP_OK) return ESP_FAIL; /* LIN2/RIN2 — SLIC handset mic */
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if (i2c_write_reg(ES8388_ADC_CTL3, 0x02) != ESP_OK) return ESP_FAIL; /* DS filter sel */
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if (i2c_write_reg(ES8388_ADC_CTL4, 0x0C) != ESP_OK) return ESP_FAIL; /* I2S 16-bit */
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if (i2c_write_reg(ES8388_ADC_CTL5, 0x02) != ESP_OK) return ESP_FAIL; /* RATIO=256 */
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if (i2c_write_reg(0x0E, 0x00) != ESP_OK) return ESP_FAIL; /* ADCCONTROL6: clear ADCSMUTE bit5 (reset default 0x30 = ADC output muted) */
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if (i2c_write_reg(ES8388_ADC_CTL8, 0x00) != ESP_OK) return ESP_FAIL; /* ADC vol L 0dB */
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if (i2c_write_reg(ES8388_ADC_CTL9, 0x00) != ESP_OK) return ESP_FAIL; /* ADC vol R 0dB */
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/* 8. DAC I2S: 16-bit I2S Philips, MCLK/256, no softmute. */
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if (i2c_write_reg(ES8388_DAC_CTL1, 0x18) != ESP_OK) return ESP_FAIL;
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if (i2c_write_reg(ES8388_DAC_CTL2, 0x02) != ESP_OK) return ESP_FAIL; /* DACLRCKDIV=256 */
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if (i2c_write_reg(ES8388_DAC_CTL3, 0x00) != ESP_OK) return ESP_FAIL; /* mute off */
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/* 9. DAC volume: 0 dB on both channels. */
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if (i2c_write_reg(ES8388_DAC_CTL4, ES8388_VOL_0DB) != ESP_OK) return ESP_FAIL;
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if (i2c_write_reg(ES8388_DAC_CTL5, ES8388_VOL_0DB) != ESP_OK) return ESP_FAIL;
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/* 10. Mixer: L→LOUT, R→ROUT (straight through, no cross-mix). */
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if (i2c_write_reg(ES8388_DAC_CTL16, 0x1B) != ESP_OK) return ESP_FAIL;
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if (i2c_write_reg(ES8388_DAC_CTL17, 0x90) != ESP_OK) return ESP_FAIL;
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if (i2c_write_reg(ES8388_DAC_CTL20, 0x90) != ESP_OK) return ESP_FAIL;
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/* 11. DACCONTROL21 (0x2B): ADC+DAC LRCK sync.
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* Espressif reference es8388_start():
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* 0xC0 = LINE mode (analog bypass, not ADC digital path)
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* 0x80 = DAC+ADC digital record+playback mode (bit7 only)
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* We want digital ADC recording + DAC playback → use 0x80. */
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if (i2c_write_reg(ES8388_DAC_CTL21, 0x80) != ESP_OK) return ESP_FAIL;
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/* 11b. Restart internal state machine (required after DACCONTROL21 change).
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* Without this pulse, the ADC clock domain may not synchronise properly.
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* Espressif reference sequence: CHIPPOWER=0xF0 then 0x00 to restart FSM. */
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if (i2c_write_reg(ES8388_CHIP_POWER, 0xF0) != ESP_OK) return ESP_FAIL;
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vTaskDelay(pdMS_TO_TICKS(5));
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if (i2c_write_reg(ES8388_CHIP_POWER, 0x00) != ESP_OK) return ESP_FAIL;
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vTaskDelay(pdMS_TO_TICKS(10));
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/* DACCONTROL23 (0x2D): VROI=0, normal output. */
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if (i2c_write_reg(ES8388_DAC_CTL23, 0x00) != ESP_OK) return ESP_FAIL;
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/* 12. Volume: OUT1L/R = 0x1E (0dB), OUT2L = 0 (speaker vol set by PA separately). */
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if (i2c_write_reg(ES8388_DAC_CTL24, 0x1E) != ESP_OK) return ESP_FAIL; /* LOUT1VOL */
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if (i2c_write_reg(ES8388_DAC_CTL25, 0x1E) != ESP_OK) return ESP_FAIL; /* ROUT1VOL */
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if (i2c_write_reg(ES8388_DAC_CTL26, 0x00) != ESP_OK) return ESP_FAIL; /* LOUT2VOL */
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/* 13. DAC power: power up DAC L+R. */
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if (i2c_write_reg(ES8388_DAC_POWER, 0x3C) != ESP_OK) return ESP_FAIL;
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/* 14. ADC power: full power-up (all Pdn bits cleared = 0x00).
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* 0x09 is the intermediate state (Espressif es8388_open end-state), but
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* the full ADC + analog input power-up requires 0x00 (Espressif es8388_start(ADC)).
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* Must come AFTER DACCONTROL21 state machine restart and ADCCONTROL6 unmute. */
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if (i2c_write_reg(ES8388_ADC_POWER, 0x00) != ESP_OK) return ESP_FAIL;
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vTaskDelay(pdMS_TO_TICKS(10)); /* let ADC analog settle after full power-up */
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/* 15. Enable PA (power amplifier for speaker). */
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gpio_set_direction(PLIP_PA_ENABLE, GPIO_MODE_OUTPUT);
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gpio_set_level(PLIP_PA_ENABLE, 1);
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/* Verify key register values to confirm ADC path is configured correctly. */
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uint8_t ctl1=0, adcpwr=0, adcinsel=0, dacctl21=0, chippower=0, adcctl3=0;
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es8388_read_reg(ES8388_CHIP_CTL1, &ctl1);
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es8388_read_reg(ES8388_ADC_POWER, &adcpwr);
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es8388_read_reg(ES8388_ADC_CTL2, &adcinsel); /* ADCCONTROL2 = input sel (0x50=LIN2) */
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es8388_read_reg(ES8388_ADC_CTL3, &adcctl3); /* ADCCONTROL3 = DS filter (0x02) */
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es8388_read_reg(ES8388_DAC_CTL21, &dacctl21); /* DACCONTROL21 = ADC+DAC LRCK sync (0xC0) */
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es8388_read_reg(ES8388_CHIP_POWER, &chippower);
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ESP_LOGI(TAG, "ES8388 regs: CTL1=0x%02X ADCPWR=0x%02X ADCINSEL=0x%02X ADCCTL3=0x%02X DACCTL21=0x%02X CHIPPOWER=0x%02X",
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ctl1, adcpwr, adcinsel, adcctl3, dacctl21, chippower);
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ESP_LOGI(TAG, "ES8388 init OK — PA enabled, DAC @ 0dB, ADC PGA +12dB, input=LIN2/RIN2 (SLIC handset), DACCTL21=0x80");
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return ESP_OK;
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}
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esp_err_t es8388_set_volume(uint8_t vol)
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{
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/* ES8388 OUTx volume registers are GAIN, not attenuation: 0x00 = -45 dB
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* (min) .. 0x21 = 0 dB (max); higher value = louder (>0x21 = mute/reserved).
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* Map 0..100 → 0x00..0x21. (The previous code inverted this, so vol=100
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* produced 0x00 = quietest — confirmed at the bench.)
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* DACCONTROL24 (0x2E)=OUT1L, 25 (0x2F)=OUT1R, 26 (0x30)=OUT2L, 27 (0x31)=OUT2R.
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* DACCONTROL21 (0x2B) is the ADC/DAC LRCK sync register — DO NOT touch here. */
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if (vol > 100) vol = 100;
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uint8_t reg_val = (uint8_t)((int)vol * 0x21 / 100);
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if (reg_val > 0x21) reg_val = 0x21;
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ESP_LOGI(TAG, "set_volume: %d%% -> reg=0x%02X (0x21=max,0dB)", vol, reg_val);
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esp_err_t r = ESP_OK;
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r |= i2c_write_reg(ES8388_DAC_CTL24, reg_val); /* OUT1 L volume */
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r |= i2c_write_reg(ES8388_DAC_CTL25, reg_val); /* OUT1 R volume */
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r |= i2c_write_reg(ES8388_DAC_CTL26, reg_val); /* OUT2 L volume */
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r |= i2c_write_reg(0x31, reg_val); /* OUT2 R volume (DACCONTROL27) */
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return r;
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}
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esp_err_t es8388_set_dac_volume(uint8_t atten)
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{
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/* DACCONTROL4 (0x04) = LDACVOL, DACCONTROL5 (0x05) = RDACVOL: DIGITAL DAC
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* volume, applied BEFORE the analog output stages. 0x00 = 0 dB, each step
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* = -0.5 dB, up to 0xC0 = -96 dB (mute). Lowering this gives analog
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* headroom while keeping the output-stage volume (es8388_set_volume) high. */
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if (atten > 0xC0) atten = 0xC0;
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ESP_LOGI(TAG, "set_dac_volume: atten=0x%02X (-%.1f dB)", atten, atten * 0.5f);
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esp_err_t r = i2c_write_reg(ES8388_DAC_CTL4, atten);
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r |= i2c_write_reg(ES8388_DAC_CTL5, atten);
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return r;
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}
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esp_err_t es8388_mute(bool mute)
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{
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uint8_t val = mute ? 0x04 : 0x00; /* bit2 = DACMUTE */
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ESP_LOGI(TAG, "mute: %s", mute ? "on" : "off");
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return i2c_write_reg(ES8388_DAC_CTL3, val);
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}
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