From 4a6fc435a73be5ff5c1e8c74681e6a613fa5ac48 Mon Sep 17 00:00:00 2001 From: clement Date: Tue, 16 Jun 2026 09:32:36 +0200 Subject: [PATCH] fix(plip): ES8388 undoc DLL regs for 16kHz ADC --- plip_voice/main/es8388.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/plip_voice/main/es8388.c b/plip_voice/main/es8388.c index 5774502..d7ed7df 100644 --- a/plip_voice/main/es8388.c +++ b/plip_voice/main/es8388.c @@ -142,6 +142,18 @@ esp_err_t es8388_init(void) /* 3b. CONTROL2 (0x01): VROI=0, LPVrefBuf=0, normal operation. */ if (i2c_write_reg(ES8388_CHIP_CTL2, 0x50) != ESP_OK) return ESP_FAIL; + /* 3c. Internal DLL stabilisation for LOW sample rates (16 kHz). UNDOCUMENTED + * registers 0x35/0x37/0x39 — the proven A252 driver (hardware/projects/ + * slic-phone Es8388Driver.cpp) sets these to "disable internal DLL for low + * sample-rate stability". WITHOUT them the ADC clock domain is unstable at + * 16 kHz and the ADC outputs a frozen DC value (capture = flat, no AC) even + * though analog signal is present on the LIN pin — exactly our symptom. The + * DAC tolerates it, which is why playback worked but capture didn't. They + * must be set here in the boot sequence (a live poke can't re-lock the DLL). */ + if (i2c_write_reg(0x35, 0xA0) != ESP_OK) return ESP_FAIL; + if (i2c_write_reg(0x37, 0xD0) != ESP_OK) return ESP_FAIL; + if (i2c_write_reg(0x39, 0xD0) != ESP_OK) return ESP_FAIL; + /* 4. Clock: MCLK divider = 256*Fs, DAC SRC = MCLK. */ if (i2c_write_reg(0x08, 0x00) != ESP_OK) return ESP_FAIL; /* MASTERMODE = slave */